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s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use document id: pmc-1990267, issue 3 pm7347 s/uni - je t tm s/uni?-jet saturn? user network interface for j2/e3/t3 data sheet released issue 3: june 2001
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 2 document id: pmc-1990267, issue 3 legal information copyright ? 2001 pmc-sierra, inc. the information is proprietary and confidential to pmc-sierra, inc., and for its customers? internal use. in any event, you cannot reproduce any part of this document, in any form, without the express written consent of pmc-sierra, inc. pmc-1990267 (r3) disclaimer none of the information contained in this document constitutes an express or implied warranty by pmc-sierra, inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of pmc-sierra, inc., or any portion thereof, referred to in this document. pmc-sierra, inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. in no event will pmc-sierra, inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not pmc-sierra, inc. has been advised of the possibility of such damage. trademarks s/uni and saturn are registerd trademarks of pmc-sierra, inc. sci-phy is a trademark of pmc-sierra, inc.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 3 document id: pmc-1990267, issue 3 contacting pmc-sierra pmc-sierra 8555 baxter place burnaby, bc canada v5a 4v7 tel: (604) 415-6000 fax: (604) 415-6200 document information: document@pmc-sierra.com corporate information: info@pmc-sierra.com technical support: apps@pmc-sierra.com web site: http://www.pmc-sierra.com
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 4 document id: pmc-1990267, issue 3 revision history issue no. issue date details of change 3 june 2001 included application examples, description, and functional description, functional timing, microprocessor timing, and a.c. timing sections. completed normal mode register and operation sections. changed all read-only ?reserved? bits to ?unused?. changed iddop values. changed thermal ?case? temperature to ?ambient?, section 11. divided pin diagram into quadrants for readability. 2 march 2000 preliminary label removed. s/uni-jet errata added. 1 april 1999 document created.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 5 document id: pmc-1990267, issue 3 table of contents 1 features.....................................................................................................................1 7 2 applications ...............................................................................................................21 3 references ................................................................................................................22 4 definitions ..................................................................................................................2 4 5 application examples ................................................................................................26 6 block diagram ...........................................................................................................28 7 description.................................................................................................................29 8 pin diagram ...............................................................................................................32 9 pin description...........................................................................................................34 10 functional description ...............................................................................................54 10.1 ds3 framer.......................................................................................................54 10.2 e3 framer .........................................................................................................56 10.3 j2 framer..........................................................................................................58 10.3.1 j2 frame find algorithms ....................................................................59 10.4 rboc bit-oriented code detector ...................................................................62 10.5 rdlc pmdl receiver ......................................................................................62 10.6 pmon performance monitor accumulator........................................................63 10.7 splr plcp layer receiver .............................................................................63 10.8 atmf atm cell delineator................................................................................64 10.9 prgd pseudo-random sequence generator/detector ..................................65 10.10 rxcp-50 receive cell processor ....................................................................66 10.11 rxff receive fifo..........................................................................................68 10.12 cppm cell and plcp performance monitor ....................................................69 10.13 ds3 transmitter ................................................................................................69 10.14 e3 transmitter...................................................................................................70 10.15 j2 transmitter ...................................................................................................71 10.16 xboc bit oriented code generator .................................................................72 10.17 tdpr pmdl transmitter ..................................................................................72 10.18 splt smds plcp layer transmitter ..............................................................73 10.19 txcp-50 transmit cell processor ....................................................................74 10.20 txff transmit fifo .........................................................................................74 10.21 ttb trail trace buffer .......................................................................................75 10.22 jtag test access port......................................................................................75
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 6 document id: pmc-1990267, issue 3 10.23 microprocessor interface ..................................................................................76 11 normal mode register description............................................................................81 12 test features description........................................................................................249 12.1 test mode 0 details.........................................................................................251 12.2 jtag test port ................................................................................................255 13 operation .................................................................................................................259 13.1 software initialization sequence.....................................................................259 13.2 register settings for basic configurations .....................................................260 13.3 plcp frame formats .....................................................................................261 13.3.1 plcp path overhead octet processing ............................................264 13.4 ds3 frame format .........................................................................................267 13.5 g.751 e3 frame format .................................................................................269 13.6 g.832 e3 frame format .................................................................................270 13.7 j2 frame format ............................................................................................271 13.8 s/uni-jet cell data structure........................................................................273 13.9 resetting the rxff and txff fifos ............................................................277 13.10 servicing interrupts .........................................................................................277 13.11 using the performance monitoring features ..................................................277 13.12 using the internal pmdl transmitter..............................................................278 13.12.1 interrupt driven mode.........................................................................279 13.12.2 tdpr interrupt routine......................................................................280 13.13 using the internal data link receiver ............................................................281 13.14 prgd pattern generation ..............................................................................285 13.14.1 generating and detecting repetitive patterns .....................................286 13.14.2 common test patterns.......................................................................286 13.15 jtag support..................................................................................................288 13.15.1 tap controller ....................................................................................289 14 functional timing.....................................................................................................295 15 absolute maximum ratings.....................................................................................319 16 d.c. characteristics.................................................................................................320 17 microprocessor interface timing characteristics ....................................................322 18 a.c. timing characteristics .....................................................................................325 19 ordering and thermal information ..........................................................................339 20 mechanical information ...........................................................................................340 notes .......................................................................................................................... .....341
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 7 document id: pmc-1990267, issue 3
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 8 document id: pmc-1990267, issue 3 list of registers register 300h: s/uni-jet configuration 1.......................................................................82 register 301h: s/uni-jet configuration 2.......................................................................85 register 302h: s/uni-jet transmit configuration ...........................................................87 register 303h: s/uni-jet receive configuration............................................................89 register 304h: s/uni-jet data link and ferf/rai control...........................................91 register 305h: s/uni-jet interrupt status.......................................................................95 register 006h: s/uni-jet identification, master reset, and global monitor update ......................................................................................................................96 register 307h: s/uni-jet clock activity monitor and interrupt identification ..................97 register 308h: splr configuration..................................................................................98 register 309h: splr interrupt enable ...........................................................................100 register 30ah: splr interrupt status ............................................................................102 register 30bh: splr status...........................................................................................104 register 30ch: splt configuration................................................................................106 register 30dh: splt control..........................................................................................109 register 30eh: splt diagnostics and g1 octet ............................................................ 111 register 30fh: splt f1 octet........................................................................................ 113 register 310h: change of pmon performance meters ................................................. 114 register 311h: pmon interrupt enable/status ............................................................... 115 register 314h: pmon lcv event count lsb................................................................ 116 register 315h: pmon lcv event count msb............................................................... 116 register 316h: pmon framing bit error event count lsb ........................................... 117 317h: pmon framing bit error event count msb......................................................... 117 register 318h: pmon excessive zero count lsb ........................................................ 118 register 319h: pmon excessive zero count msb ....................................................... 118 register 31ah: pmon parity error event count lsb .................................................... 119 register 31bh: pmon parity error event count msb ................................................... 119 register 31ch: pmon path parity error event count lsb............................................120 register 31dh: pmon path parity error event count msb...........................................120 register 31eh: pmon febe/j2-exzs event count lsb..............................................121 register 31fh: pmon febe/j2-exzs event count msb.............................................121 register 321h: cppm change of cppm performance meters ......................................122 register 322h: cppm b1 error count lsb ....................................................................123 register 323h: cppm b1 error count msb ...................................................................123
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 9 document id: pmc-1990267, issue 3 register 324h: cppm framing error event count lsb .................................................124 register 325h: cppm framing error event count msb ................................................124 register 326h: cppm febe count lsb ........................................................................125 register 327h: cppm febe count msb .......................................................................125 register 330h: ds3 frmr configuration.......................................................................126 register 331h: ds3 frmr interrupt enable (ace=0) ...................................................128 register 331h: ds3 frmr additional configuration register .......................................130 register 332h: ds3 frmr interrupt status....................................................................133 register 333h: ds3 frmr status ..................................................................................135 register 334h: ds3 tran configuration .......................................................................137 register 335h: ds3 tran diagnostic............................................................................139 register 338h: e3 frmr framing options ....................................................................141 register 339h: e3 frmr maintenance options ............................................................143 register 33ah: e3 frmr framing interrupt enable ......................................................145 register 33bh: e3 frmr framing interrupt indication and status ................................146 register 33ch: e3 frmr maintenance event interrupt enable ....................................148 register 33dh: e3 frmr maintenance event interrupt indication ................................150 register 33eh: e3 frmr maintenance event status ....................................................152 register 340h: e3 tran framing options.....................................................................154 register 341h: e3 tran status and diagnostic options...............................................155 register 342h: e3 tran bip-8 error mask....................................................................157 register 343h: e3 tran maintenance and adaptation options ....................................158 register 344h: j2-frmr configuration..........................................................................160 register 345h: j2-frmr status .....................................................................................162 register 346h: j2-frmr alarm interrupt enable ...........................................................163 register 347h: j2-frmr alarm interrupt status ............................................................165 register 348h: j2-frmr error/xbit interrupt enable .....................................................167 register 349h: j2-frmr error/xbit interrupt status ......................................................169 register 34ch: j2-tran configuration..........................................................................171 register 34dh: j2-tran diagnostic ..............................................................................172 register 34eh: j2-tran ts97 signaling.......................................................................173 register 34fh: j2-tran ts98 signaling .......................................................................174 register 350h: rdlc configuration ...............................................................................175 register 351h: rdlc interrupt control...........................................................................177 register 352h: rdlc status...........................................................................................178
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 10 document id: pmc-1990267, issue 3 register 353h: rdlc data .............................................................................................180 register 354h: rdlc primary address match ...............................................................181 register 355h: rdlc secondary address match ..........................................................182 register 358h: tdpr configuration ...............................................................................183 register 359h: tdpr upper transmit threshold ...........................................................185 register 35ah: tdpr lower interrupt threshold ...........................................................186 register 35bh: tdpr interrupt enable...........................................................................187 register 35ch: tdpr interrupt status/udr clear .........................................................188 register 35dh: tdpr transmit data..............................................................................190 register 360h: rxcp-50 configuration 1.......................................................................191 register 361h: rxcp-50 configuration 2.......................................................................193 register 362h: rxcp-50 fifo/utopia control & configuration ..................................195 register 363h: rxcp-50 interrupt enables and counter status....................................197 register 364h: rxcp-50 status/interrupt status............................................................199 register 365h: rxcp-50 lcd count threshold (msb) .................................................201 register 366h: rxcp-50 lcd count threshold (lsb) ..................................................201 register 367h: rxcp-50 idle cell header pattern.........................................................203 register 368h: rxcp-50 idle cell header mask............................................................204 register 369h: rxcp-50 corrected hcs error count ...................................................205 register 36ah: rxcp-50 uncorrected hcs error count...............................................206 register 36bh: rxcp-50 receive cell counter (lsb) ..................................................207 register 36ch: rxcp-50 receive cell counter ............................................................207 register 36dh: rxcp-50 receive cell counter (msb) .................................................208 register 36eh: rxcp-50 idle cell counter (lsb)..........................................................209 register 36fh: rxcp-50 idle cell counter ....................................................................209 register 370h: rxcp-50 idle cell counter (msb) .........................................................210 register 380h: txcp-50 configuration 1 ....................................................................... 211 register 381h: txcp-50 configuration 2 .......................................................................213 register 382h: txcp-50 cell count status....................................................................215 register 383h: txcp-50 interrupt enable/status ...........................................................216 register 384h: txcp-50 idle cell header control .........................................................218 register 385h: txcp-50 idle cell payload control........................................................219 register 386h: txcp-50 transmit cell count (lsb)......................................................220 register 387h: txcp-50 transmit cell count ................................................................220 register 388h: txcp-50 transmit cell count (msb).....................................................221
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 11 document id: pmc-1990267, issue 3 register 390h: ttb control ............................................................................................222 register 391h: ttb trail trace identifier status .............................................................224 register 392h: ttb indirect address..............................................................................225 register 393h: ttb indirect data ...................................................................................226 register 394h: ttb expected payload type label ........................................................227 register 395h: ttb payload type label control/status ................................................228 register 398h: rboc configuration/interrupt enable....................................................230 register 399h: rboc interrupt status............................................................................231 register 39ah: xboc code ...........................................................................................232 register 39bh: s/uni-jet miscellaneous ......................................................................233 register 39ch: s/uni-jet frmr lof status. ..............................................................235 register 3a0h: prgd control ........................................................................................237 register 3a1h: prgd interrupt enable/status ...............................................................239 register 3a2h: prgd length.........................................................................................241 register 3a3h: prgd tap ..............................................................................................242 register 3a4h: prgd error insertion register ..............................................................243 register 3a8h: pattern insertion #1................................................................................244 register 3a9h: pattern insertion #2................................................................................244 register 3aah: pattern insertion #3 ...............................................................................245 register 3abh: pattern insertion #4 ...............................................................................245 register 3ach: prgd pattern detector #1....................................................................246 register 3adh: prgd pattern detector #2....................................................................246 register 3aeh: prgd pattern detector #3 ....................................................................247 register 3afh: prgd pattern detector #4 ....................................................................247 register 40ch: s/uni-jet identification register ..........................................................248
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 12 document id: pmc-1990267, issue 3 list of figures figure 1 s/uni-jet operating as an atm phy in an atm switch ................................26 figure 2 s/uni-jet operating as a framer device in frame relay equipment............27 figure 3 block diagram ...................................................................................................28 figure 4 framing algorithm (crc_refr = 0) ................................................................60 figure 5 framing algorithm (crc_refr = 1)................................................................61 figure 6 cell delineation state diagram .........................................................................65 figure 7 hcs verification state diagram........................................................................68 figure 8 ds3 plcp frame format ...............................................................................262 figure 9 ds1 plcp frame format ...............................................................................262 figure 10 g.751 e3 plcp frame format.....................................................................263 figure 11 e1 plcp frame format................................................................................264 figure 12 ds3 frame structure ....................................................................................267 figure 13 g.751 e3 frame structure ............................................................................269 figure 14 g.832 e3 frame structure ............................................................................270 figure 15 j2 frame structure .......................................................................................272 figure 16 16-bit wide, 26-byte word structure.............................................................273 figure 17 16-bit wide, 27-byte word structure.............................................................274 figure 18 8-bit wide, 52-byte word structure...............................................................275 figure 19 8-bit wide, 53-byte word structure...............................................................276 figure 20 typical data frame.......................................................................................284 figure 21 example multi-packet operational sequence ..............................................284 figure 22 prgd pattern generator ..............................................................................285 figure 23 boundary scan architecture .........................................................................288 figure 24 tap controller finite state machine.............................................................290 figure 25 input observation cell (in_cell) ................................................................293 figure 26 output cell (out_cell) ..............................................................................293 figure 27 bi-directional cell (io_cell) ........................................................................294 figure 28 layout of output enable and bi-directional cells .........................................294 figure 29 receive ds1 stream.....................................................................................295 figure 30 receive e1 stream .......................................................................................295 figure 31 receive bipolar ds3 stream ........................................................................296 figure 32 receive unipolar ds3 stream ......................................................................296 figure 33 receive bipolar e3 stream ...........................................................................296
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 13 document id: pmc-1990267, issue 3 figure 34 receive unipolar e3 stream.........................................................................297 figure 35 receive bipolar j2 stream ...........................................................................297 figure 36 receive unipolar j2 stream .........................................................................298 figure 37 generic receive stream ...............................................................................298 figure 38 receive ds3 overhead ................................................................................299 figure 39 receive g.832 e3 overhead ........................................................................300 figure 40 receive g.751 e3 overhead ........................................................................300 figure 41 receive j2 overhead....................................................................................301 figure 42 receive plcp overhead ..............................................................................301 figure 43 transmit ds1 stream....................................................................................302 figure 44 transmit e1 stream ......................................................................................302 figure 45 transmit bipolar ds3 stream .......................................................................303 figure 46 transmit unipolar ds3 stream .....................................................................303 figure 47 transmit bipolar e3 stream ..........................................................................304 figure 48 transmit unipolar e3 stream........................................................................304 figure 49 transmit bipolar j2 stream ..........................................................................305 figure 50 transmit unipolar j2 stream ........................................................................305 figure 51 generic transmit stream ..............................................................................306 figure 52 transmit ds3 overhead ...............................................................................307 figure 53 transmit g.832 e3 overhead .......................................................................308 figure 54 transmit g.751 e3 overhead .......................................................................309 figure 55 transmit j2 overhead...................................................................................309 figure 56 transmit plcp overhead .............................................................................310 figure 57 framer mode ds3 transmit input stream....................................................311 figure 58 framer mode ds3 transmit input stream with tgapclk..........................311 figure 59 framer mode ds3 receive output stream ..................................................311 figure 60 framer mode ds3 receive output stream with rgapclk ........................312 figure 61 framer mode g.751 e3 transmit input stream ...........................................312 figure 62 framer mode g.751 e3 transmit input stream with tgapclk .................312 figure 63 framer mode g.751 e3 receive output stream..........................................313 figure 64 framer mode g.751 e3 receive output stream with rgapclk ................313 figure 65 framer mode g.832 e3 transmit input stream ...........................................314 figure 66 framer mode g.832 e3 transmit input stream with tgapclk .................314 figure 67 framer mode g.832 e3 receive output stream..........................................314 figure 68 framer mode g.832 e3 receive output stream with rgapclk ................314
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 14 document id: pmc-1990267, issue 3 figure 69 framer mode j2 transmit input stream .......................................................315 figure 70 framer mode j2 transmit input stream with tgapclk.............................315 figure 71 framer mode j2 receive output stream .....................................................316 figure 72 framer mode j2 receive output stream with rgapclk ...........................316 figure 73 multi-phy polling and addressing transmit cell interface...........................317 figure 74 multi-phy polling and addressing receive cell interface............................318 figure 75 microprocessor interface read timing .........................................................322 figure 76 microprocessor interface write timing .........................................................324 figure 77 rstb timing.................................................................................................325 figure 78 transmit atm cell interface timing .............................................................326 figure 79 receive atm cell interface timing ..............................................................328 figure 80 transmit interface timing .............................................................................330 figure 81 receive interface timing ..............................................................................335 figure 82 jtag port interface timing...........................................................................337
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 15 document id: pmc-1990267, issue 3 list of tables table 1 supported operating formats............................................................................17 table 2 transmission system sublayer processing acceptance and output ................29 table 3 summary of receive detection features ..........................................................29 table 4 multiframe format ..............................................................................................58 table 5 c1 octet pattern.................................................................................................74 table 6 register memory map ........................................................................................76 table 7 statsel[2:0] options .......................................................................................86 table 8 tfrm[1:0] transmit frame structure configurations ........................................88 table 9 lof[1:0] integration period configuration .........................................................90 table 10 rfrm[1:0] receive frame structure configurations ......................................90 table 11 splr form[1:0] configurations .....................................................................99 table 12 plcp lof declaration/removal times.........................................................104 table 13 splt form[1:0] configurations ...................................................................107 table 14 ds3 frmr exzs/lcv count configurations................................................131 table 15 ds3 frmr ais configurations ......................................................................132 table 16 e3 frmr format[1:0] configurations ........................................................141 table 17 e3 tran format[1:0] configurations.........................................................154 table 18 j2 frmr los threshold configurations.......................................................161 table 19 rdlc pbs[2:0] data status...........................................................................178 table 20 rxcp-50 hcs filtering configurations .........................................................193 table 21 rxcp-50 cell delineation algorithm base ....................................................193 table 22 rxcp-50 lcd integration periods.................................................................201 table 23 txcp-50 fifo depth configurations ............................................................213 table 24 ttb payload type match configurations ......................................................227 table 25 prgd pattern detector register configuration.............................................237 table 26 prgd generated bit error rate configurations............................................243 table 27 test mode register memory map ..................................................................249 table 28 test mode 0 input read address locations .................................................251 table 29 test mode 0 output write address locations ...............................................253 table 30 instruction register ........................................................................................255 table 31 identification register.....................................................................................256 table 32 boundary scan register ................................................................................256 table 33 register settings for basic configurations.....................................................260
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 16 document id: pmc-1990267, issue 3 table 34 plcp overhead processing ..........................................................................264 table 35 plcp path overhead identifier codes ..........................................................266 table 36 ds3 plcp trailer length...............................................................................266 table 37 e3 plcp trailer length .................................................................................267 table 38 ds3 frame overhead operation ...................................................................268 table 39 g.751 e3 frame overhead operation ...........................................................269 table 40 g.832 e3 frame overhead operation ...........................................................270 table 41 j2 frame overhead operation.......................................................................272 table 42 pseudo random pattern generation (ps bit = 0)..........................................286 table 43 repetitive pattern generation (ps bit = 1).....................................................287 table 44 ds3 receive overhead bits...........................................................................299 table 45 ds3 transmit overhead bits.........................................................................307 table 46 absolute maximum ratings............................................................................319 table 47 dc characteristics .........................................................................................320 table 48 microprocessor interface read access (figure 75).......................................322 table 49 microprocessor interface write access (figure 76) .......................................323 table 50 rstb timing (figure 77) ...............................................................................325 table 51 transmit atm cell interface timing (figure 78) ............................................325 table 52 receive atm cell interface timing (figure 79) .............................................327 table 53 transmit interface timing (figure 80)............................................................329 table 54 receive interface timing (figure 81).............................................................334 table 55 jtag port interface (refer to figure 82) .......................................................336 table 56 packaging information....................................................................................339 table 57 thermal information .......................................................................................339
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 17 document id: pmc-1990267, issue 3 1 features the s/uni?-jet is a single chip asynchronous transfer mode (atm) user network interface (uni) operating at 44.736 mbit/s, 34.368 mbit/s, and 6.312 mbit/s that: ? conforms to af-physical (phy)-0054.000, af-phy-0034.000 and af-phy-0029.000. ? implements atm direct cell mapping into ds1, ds3, e1, e3, and j2 transmission systems according to itu-t recommendation g.804. ? provides a utopia level 2 compatible atm-phy interface. ? implements the physical layer convergence protocol (plcp) for ds1 and ds3 transmission systems according to the atm forum user network interface specification and ansi ta- tsy-000773, ta-tsy-000772, and e1 and e3 transmission systems according to the etsi 300-269 and etsi 300-270. ? supports switched multi-megabit data service (smds) and atm mappings into various rate transmission systems as shown in table 1: table 1 supported operating formats rate format framer only smds plcp mapping atm direct mapping c-bit parity yes yes yes t3 (44.736 mbit/s) m23 yes yes yes g.751 yes yes yes e3 (34.368 mbit/s) g.832 yes n/a yes j2 (6.312 mbit/s) g.704 & ntt yes n/a yes crc-4 external yes yes e1 (2.048 mbit/s) pcm30 external yes yes esf external yes yes t1 (1.544 mbit/s) sf external yes yes arbitrary cell rate (up to 52 mbit/s) bypass n/a yes ? implements the atm physical layer for broadband isdn according to itu-t recommendation i.432. ? provides on-chip ds3, e3 (g.751 and g.832), and j2 framers. ? is configurable for sole ds3, e3, or j2 framer use. note: when configured to operate as a ds3, e3, or j2 framer, gapped transmit and receive clocks can be optionally generated for interface to devices which only need access to payload data bits. ? provides support for an arbitrary rate external transmission system interface up to a maximum rate of 52 mbit/s, which enables the s/uni-jet to be used as an atm cell delineator.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 18 document id: pmc-1990267, issue 3 ? uses the pmc-sierra? pm4351 comet, pm4341 t1xc and pm6341 e1xc t1 and e1 framer/line interface chips for ds1 and e1 applications. ? provides programmable pseudo-random test pattern generation, detection, and analysis features. ? provides integral transmit and receive hdlc controller with 128-byte fifo depth. ? provides performance monitoring counters suitable for accumulation periods of up to 1 second. ? provides an 8-bit microprocessor interface for configuration, control and status monitoring. ? provides a standard 5 signal p1149.1 jtag test port for boundary scan board test purposes. ? uses low power 3.3v cmos technology with 5v tolerant inputs. ? is available in a 256-pin sbga package (27mm x 27mm). the receiver section of the s/uni-jet: ? provides frame synchronization for the m23 or c-bit parity ds3 applications and alarm detection. also: accumulates line code violations, framing errors, parity errors, path parity errors and febe events. detects far end alarm channel codes. provides an integral hdlc receiver to terminate the path maintenance data link. ? provides frame synchronization for the g.751 or g.832 e3 applications and alarm detection. also: accumulates line code violations, framing errors, parity errors, and febe events. detects the trail trace in g.832, the trail trace is detected. provides an integral hdlc receiver is provided to terminate either the network requirement or the general purpose data link. ? provides frame synchronization for g.704 and ntt 6.312 mbit/s j2 applications and alarm detection. also: accumulates line code violations, framing errors, and crc parity errors. provides an integral hdlc receiver to terminate the data link. ? provides frame synchronization, cell delineation and extraction for ds3, g.751 e3, g.832 e3, and g.704 and ntt j2 atm direct-mapped formats. ? provides plcp frame synchronization, path overhead extraction, and cell extraction for ds1 plcp, ds3 plcp, e1 plcp, and g.751 e3 plcp formatted streams. ? provides a 50 mhz 8-bit wide or 16-bit wide utopia fifo buffer in the receive path with parity support, and multi-phy (level 2) control signals. ? provides atm framing using cell delineation. note: atm cell delineation may optionally be disabled to allow passing of all cell bytes regardless of cell delineation status.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 19 document id: pmc-1990267, issue 3 ? provides cell descrambling, header check sequence (hcs) error detection, idle cell filtering, header descrambling (for use with ppp packets), and accumulates the number of received idle cells, the number of received cells written to the fifo, and the number of hcs errors. ? provides a four cell fifo for rate decoupling between the line, and a higher layer processing entity. fifo latency may be reduced by changing the number of operational cell fifos. ? provides a receive hdlc controller with a 128-byte fifo to accumulate data link information. ? provides detection of yellow alarm and loss of frame (lof), and accumulates bip-8 errors, framing errors and febe events. ? provides programmable pseudo-random test-sequence detection (up to 2 32 -1 bit length patterns conforming to itu-t o.151 standards) and analysis features. the transmitter section of the s/uni-jet: ? provides frame insertion for the m23 or c-bit parity ds3 applications, alarm insertion, and diagnostic features. also: optionally inserts far end alarm channel codes. provides an integral hdlc transmitter is provided to insert the path maintenance data link. ? provides frame insertion for the g.751 or g.832 e3 applications, alarm insertion, and diagnostic features. also: inserts the trail trace for g.832 provides an integral hdlc transmitter to insert either the network requirement or the general purpose data link. ? provides frame insertion for g.704 6.312 mbit/s j2 applications, alarm insertion, and diagnostic features, and also an integral hdlc transmitter to insert the path maintenance data link. ? provides frame insertion and path overhead insertion for ds1, ds3, e1 or e3 based plcp formats, and also alarm insertion and diagnostic features. ? provides a 50 mhz 8-bit wide or 16-bit wide utopia fifo buffer in the transmit path with parity support and multi-phy (level 2) control signals. ? provides optional atm cell scrambling, header scrambling (for use with ppp packets), hcs generation/insertion, programmable idle cell insertion, diagnostics features and accumulates transmitted cells read from the fifo. ? provides a four cell fifo for rate decoupling between the line and a higher layer processing entity. fifo latency may be reduced by changing the number of operational cells in the fifo. ? provides a transmit hdlc controller with a 128-byte fifo. ? provides an 8 khz reference input for locking the transmit plcp frame rate to an externally applied frame reference.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 20 document id: pmc-1990267, issue 3 ? provides programmable pseudo-random test sequence generation (up to 2 32 -1 bit length sequences conforming to itu-t o.151 standards). diagnostic abilities include single bit error insertion or error insertion at bit error rates ranging from 10 -1 to 10 -7 . the bypass and loopback features of the s/uni-jet: ? allow bypassing of the ds3, e3, and j2 framers to enable transmission system sublayer processing by an external device. ? allow bypassing of the plcp and atm functions to enable use of the s/uni-jet as a ds3, e3, or j2 framer. ? provide diagnostic loopbacks, line loopbacks, and payload loopbacks.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 21 document id: pmc-1990267, issue 3 2 applications ? atm or smds switches, multiplexers, and routers ? sonet/sdh mux e3/ds3 tributary interfaces ? pdh mux j2/e3/ds3 line interfaces ? ds3/e3/j2 digital cross connect interfaces ? ds3/e3/j2 ppp internet access interfaces ? ds3/e3/j2 frame relay interfaces ? dslam uplinks
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 22 document id: pmc-1990267, issue 3 3 references ? ansi t1.627 - 1993, "broadband isdn - atm layer functionality and specification". ? ansi t1.107a - 1990, "digital hierarchy - supplement to formats specifications (ds3 format applications)". ? ansi t1.107 - 1995, "digital hierarchy - formats specifications". ? ansi t1.646 - 1995, "broadband isdn - physical layer specification for user-network interfaces including ds1/atm". ? atm forum - atm user-network interface specification, v3.1, october, 1995. ? atm forum - ?utopia, an atm phy interface specification, level 2, version 1?, june, 1995. ? atm forum, af-phy-0034.000, "e3 (34,368 kbps) physical layer interface", august, 1995. ? atm forum, af-phy-0054.000, "ds3 physical layer interface specification", january, 1996. ? atm forum, af-phy-0029.000, "6,312 kbps uni specification, version 1.0", june 1995. ? bell communications research, ta-tsy-000773 - ?local access system generic requirements, objectives, and interface in support of switched multi-megabit data service? issue 2, march 1990 and supplement 1, december 1990. ? ets 300 269 draft standard t/na(91)17 - ?metropolitan area network physical layer convergence procedure for 2.048 mbit/s?, april 1994. ? ets 300 270 draft standard t/na(91)18 - ?metropolitan area network physical layer convergence procedure for 34.368 mbit/s?, april 1994. ? itu-t recommendation o.151 - "error performance measuring equipment operating at the primary rate and above", october, 1992. ? itu-t recommendation i.432 - "b-isdn user-network interface - physical layer specification", 1993 ? itu-t recommendation g.703 - "physical/electrical characteristics of hierarchical digital interfaces", 1991. ? itu-t recommendation g.704 - "general aspects of digital transmission systems; terminal equipment - synchronous frame structures used at 1544, 6312, 2048, 8488 and 44 736 kbit/s hierarchical levels", july, 1995. ? itu-t recommendation g.751 - ccitt blue book fasc. iii.4, "digital multiplex equipment operating at the third order bit rate of 34,368 kbit/s and the fourth order bit rate of 139,264 kbit/s and using positive justification", 1988. ? itu-t draft recommendation g.775 - "loss of signal (los) and alarm indication signal (ais) defect detection and clearance criteria", october 1993. ? itu-t recommendation g.804 - "atm cell mapping into plesiochronous digital hierarchy (pdh)", 1993.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 23 document id: pmc-1990267, issue 3 ? itu-t recommendation g.832 - "transport of sdh elements on pdh networks: frame and multiplexing structures", 1993. ? itu-t recommendation q.921 - "isdn user-network interface - data link layer specification", march, 1993. ? ntt technical reference, "ntt technical reference for high-speed digital leased circuit services", 1991.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 24 document id: pmc-1990267, issue 3 4 definitions the following table defines the abbreviations for the s/uni-jet. aic application identification channel ais alarm indication signal atm asynchronous transfer mode bip bit interleaved parity cmos complementary metal oxide semiconductor cofa change of frame alignment cperr path parity error crc cyclic redundancy check dslam dsl access multiplexer ds1 digital signal level 1 ds3 digital signal level 3 exzs excess zeros f-bit framing bit fas framing alignment signal feac far-end alarm control febe far-end block error ferf far end receive failure ferr framing bit error fifo first-in first-out hcs header check sequence hdlc high-level data link control isdn integrated services digital network itu international telecommunications union jtag joint test action group lcd loss of cell delineation lcv line code violation lof loss of frame los loss of signal nrz non return to zero oof out of frame perr parity error phy physical layer plcp physical layer convergence procedure pmdl path maintenance data link pmon performance monitor pos packet over sonet ppp point-to-point protocol
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 25 document id: pmc-1990267, issue 3 rai receive alarm indication rboc bit oriented code detector rdlc data link receiver red receive error detection sbga super ball grid array sci-phy tm saturn? compatible interface specification for phy and atm layer devices smds switched multi-megabit data service sonet synchronous optical network tap test access port tsb telecom system block ttb trail trace buffer
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 26 document id: pmc-1990267, issue 3 5 application examples the s/uni-jet is configurable as: ? an atm device ? a j2/e3/t3 framer ? a cell processor as an atm-phy layer device, the s/uni-jet connects on the line side to one j2/e3/t3 line interface unit and on the system side, it interfaces with an atm layer device, such as the pm7322 rcmp-800, over an 8- or 16-bit wide utopia level 2 interface. refer to figure 1. figure 1 s/uni-jet operating as an atm phy in an atm switch as a j2/e3/t3 framer, the s/uni-jet can be used in router, frame relay switch, and multiplexer applications. refer to figure 2. t1/e1 line card pm4314 qdsx j2/e3/t3 line card j2/e3/t3 liu pm7347 s/uni-jet atm switch core switch fabric pm7322 rcmp-800 egress device oc-12 line card pmd oc-3 line cards pm5355 s/uni-622 pm5346 s/uni-lite pm7348 s/uni- dual pm5347 s/uni-plus pm7344 s/uni-mph utopia bus utopia bus
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 27 document id: pmc-1990267, issue 3 figure 2 s/uni-jet operating as a framer device in frame relay equipment in an unchannelized j2/e3/t3 line card, the s/uni-jet directly connects to one pm7366 freedm-8 hdlc controller. each freedm-8 can process two high-speed links such as t3 and e3, or can process up to eight lower speed links such as j2. the s/uni-jet gaps all the overhead bits so that only the payload data is passed to and from freedm-8. on the line side, the s/uni- jet is connected to one j2/e3/t3 line interface unit. on the system side, the s/uni-jet interfaces with a data link device over a serial bit interface. pci bus 8 port channelized t1 card pm4314 qdsx pm4388 toctl pm7366 freedm-8 28 port unchannelized t1 card (m13) ds-3 liu pm8313 d3mx pm4388 toctl pm7364 freedm- 32 4 port channelized e1 card pm4314 qdsx pm6344 equad pm7366 freedm-8 ip switch/router core switch fabric processor packet memory unchannelized j2/e3/t3 card j2/e3/t3 liu pm7366 freedm-8 pm7347 s/uni- jet pci bus access side uplink side
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 28 document id: pmc-1990267, issue 3 6 block diagram figure 3 block diagram splt transmit atm and plcp framer cppm plcp/cell performance monitor prgd ber tester txcp_50 tx cell processor rxff rx 4 cell fifo ieee p1149.1 jtag test access port frmstat rpohclk/rsclk/rgapclk ref8ko/rpohfp/rfpo/rmfpo rpoh/rovrhd lcd/rdato rohfp rohclk roh microprocessor interface d[7.0] wrb csb ale a[10.0] rdb rstb intb tms tdi tck tdo trstb frmr j2, e3, or ds3 receive framer line decode tran j2, e3, or ds3 transmit framer xboc tx feac tdpr tx hdlc tx o/h access 1/2 ttb tx trail buffer tohfp tohclk toh tohins rboc rx feac rdlc rx hdlc pmon perfor. monitor rx o/h access 1/2 ttb rx trail buffer line encode tclk tneg/tohm tpos/tdato rneg/rlcv/rohm rpos/rdati rclk rxcp_50 rx cell processor system i/f dtca tfclk phy_adr[2.0] atm8 rfclk renb tadr[2.0] tenb tca tsoc tprty tdat[15.0] radr[2.0] rca rsoc rdat[15.0] rprty drca tpohins tpoh/tdati tiohm/tfpi/tmfpi ticlk tpohclk tpohfp/tfpo/tmfpo/tgapclk/tcell ref8ki atmf/splr receive atm and plcp framer txff tx 4 cell fifo
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 29 document id: pmc-1990267, issue 3 7 description the pm7346 s/uni-jet is an atm physical layer processor with integrated ds3, e3, and j2 framers. it supports plcp sublayer ds1, ds3, e1, and e3 processing and atm cell delineation. the s/uni-jet contains: ? an integral ds3 framer that provides ds3 framing and error accumulation in accordance with ansi t1.107, and t1.107a. ? an integral e3 framer that provide e3 framing in accordance with itu-t recommendations g.832 and g.751. ? an integral j2 framer that provide j2 framing in accordance with itu-t recommendation g.704 and i.432. when configured for various transmission system sublayer processing, the s/uni-jet accepts and outputs the appropriate type of bipolar and unipolar signals as described in table 2: table 2 transmission system sublayer processing acceptance and output transmission system sublayer processing acceptance and output ds3 accepts and outputs both digital b3zs-encoded bipolar and unipolar signals compatible with m23 and c-bit parity applications. e3 accepts and outputs both hdb3-encoded bipolar and unipolar signals compatible with g.751 and g.832 applications. j2 accepts and outputs both b8zs-encoded bipolar and unipolar signals compliant with g.704 and ntt 6.312 mbit/s applications. ds1, or e1 accepts and outputs outputs unipolar signals with appropriate clock and frame pulse signals for physical sublayer processing. other transmission systems provides a generic interface for physical sublayer processing. in the ds3 receive direction, the s/uni-jet frames to ds3 signals with a maximum average reframe time of 1.5 ms and detects line code violations (lcv), loss of signal (los), framing bit errors, parity errors, path parity errors, alarm indication signals (ais), far end receive failure (ferf), and idle code. the ds3 overhead bits are extracted and presented on serial outputs. when in c-bit parity mode, the path maintenance data link (pmdl) and the far end alarm and control (feac) channels are extracted. hdlc receivers are provided for pmdl support. valid bit-oriented codes in the feac channels are also detected and are available through the microprocessor port. table 3 summary of receive detection features transmission system sublayer processing transmit or receive detected features ds3 receive lcv, los, framing bit errors, parity errors, path parity errors, ais, ferf, and idle code e3 receive lcv, los, framing bit errors, ais, and rai
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 30 document id: pmc-1990267, issue 3 transmission system sublayer processing transmit or receive detected features j2 receive lcv, los, lof, framing bit errors, physical layer ais, payload ais, crc-5 errors, remote end alarm, and rai in the e3 receive direction, the s/uni-jet frames to g.751 and g.832 e3 signals with a maximum average reframe times of 135 s for g.751 frames and 250 s for g.832 frames. lcvs, los, framing bit errors, ais, and remote alarm indication (rai) are detected. further, when processing g.832 formatted data, parity errors, far end receive failure, and far end block errors are also detected; and the trail trace message can be extracted and made available through the microprocessor port. hdlc receivers are provided for either the g.832 network requirement or the g.832 general purpose data link support. in the j2 receive direction, the s/uni-jet frames to g.704 6.312 mhz signals with a maximum average reframe time of 5.07 ms. an alternate framing algorithm that uses the crc-5 bits to rule out 99.9% of all static mimic framing patterns is available with a maximum average reframe time of 10.22 ms when operating with a 10 - 4 bit error rate. the alternate framing algorithm can be selected by the crc_refr bit in the j2-frmr configuration register. lcv, los, loss of frame (lof), framing bit errors, physical layer ais, payload ais, crc-5 errors, remote end alarm, and rai are detected. hdlc receivers are provided for data link support. error event accumulation is also provided by the s/uni-jet. framing bit errors, lcv, parity errors, path parity errors, and far end block errors (febe) are accumulated, when appropriate, in saturating counters for ds3, e3, and j2 frames. lof detection for ds3, e3, and j2 is provided as recommended by itu-t g.783 with integration times of 1ms, 2ms, and 3ms. in the ds3 transmit direction, the s/uni-jet inserts ds3 framing, x and p bits. when enabled for c-bit parity operation, bit-oriented code transmitters and hdlc transmitters are provided for the insertion of feac channels and the pmdl in the appropriate overhead bits. ais can be inserted by using internal register bits and other status signals such as the idle signal can be inserted when enabled by internal register bits. when m23 operation is selected, the c-bit parity id bit (the first c-bit of the first m sub-frame) is forced to toggle so that downstream equipment will not confuse an m23-formatted stream with stuck-at 1 c-bits for c-bit parity application. in the e3 transmit direction, the s/uni-jet inserts e3 framing in either g.832 or g.751 format. when enabled for g.832 operation, an hdlc transmitter is provided so that the network requirement or general purpose data link is inserted into the appropriate overhead bits. the ais and other status signals can be inserted by internal register bits. in the j2 transmit direction, the s/uni-jet inserts j2 6.312 mbit/s g.704 framing. hdlc transmitters are provided the data links are inserted. crc-5 check bits are calculated and inserted into the j2 multiframe. external pins are provided so that any of the overhead bits within the j2 frame can be overwritten. the s/uni-jet also supports diagnostic options that allow it to insert, when appropriate, the transmit framing format, parity or path parity errors, f-bit framing errors, m-bit framing errors, invalid x or p-bits, lcv, all-zeros, ais, rais, and remote end alarms.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 31 document id: pmc-1990267, issue 3 the s/uni-jet provides cell delineation for atm cells using the plcp framing format, or by using the header check sequence octet in the atm cell header as specified by itu-t recommendation i.432. ds1, ds3, e1, and e3-based plcp frame formats can be processed. non-plcp-based cell delineation is done with either bit, nibble, or byte-wide search algorithms depending on the line interface used. an interface consistent with the generic physical interface defined by itu-t recommendation i.432 is provided for arbitrary rates up to 52 mbit/s. this interface is used for phy layer support for transmission systems that do not have an associated plcp sublayer, or to provide an efficient means of directly mapping atm cells to existing transmission system formats (such as ds3 and ds1). in the plcp receive direction, framing, path overhead extraction, and cell extraction is provided. bip-8 error events, frame octet error events, and febe events are accumulated. in the plcp transmit direction, the s/uni-jet provides overhead insertion using inputs or internal registers, ds3 nibble and e3 byte stuffing, automatic bip-8 octet generation and insertion, and automatic febe insertion. diagnostic features for bip-8 error, framing error and febe insertion are also supported. in the cell receive path, idle cells may be dropped according to a programmable filter. by default, incoming cells with single bit hcs errors are corrected and written to the fifo buffer. optionally, cells can be dropped upon detection of a hcs error. cell delineation may optionally be disabled to allow all cells to pass, regardless of cell delineation status. the atm cell payloads are optionally descrambled. atm cell headers may optionally be descrambled (for use with ppp packets). assigned cells containing no detectable hcs errors are written to a fifo buffer. cell data is read from the fifo using a synchronous 50 mhz 8-bit wide or 16-bit wide sci-phy tm and utopia level 2-compatible interface. cell data parity is also provided. counts of error-free assigned cells, and cells containing hcs errors are accumulated independently for performance monitoring purposes. in the cell transmit path, cell data is written to a fifo buffer using a synchronous 50 mhz 8-bit wide or 16-bit wide sci-phy tm compatible interface. cell data parity is also examined for errors. idle cells are automatically inserted when the fifo contains less than one full cell. hcs generation, cell payload scrambling, and cell header scrambling (for use with ppp packets) are optionally provided. counts of transmitted cells are accumulated for performance monitoring purposes. both receive and transmit cell fifos provide buffering for four cells. the fifos provide the rate matching interface between the higher layer atm entity and the s/uni-jet. the s/uni-jet is configured, controlled, and monitored by a generic 8-bit microprocessor bus through which all internal registers are accessed. all sources of interrupts can be identified, acknowledged, or masked with this interface. the s/uni-jet requires a software initialization sequence in order to guarantee proper device operation and long term reliability. please refer to section 13.1 of this document for the details on how to program this sequence.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 32 document id: pmc-1990267, issue 3 8 pin diagram the s/uni-jet is packaged in a 256-pin sbga package with a body size of 27 mm by 27 mm and a pin pitch of 1.27 mm. quadrant a11/a20 to k11/k20 20 19 18 17 16 15 14 13 12 11 a vss vss vss tdati[10] tdati[14] d[1] d[5] vss a[3] a[7] a b vss vdd vdd tdati[9] tdati[13] d[0] d[4] a[0] a[2] a[6] b c vss vdd vdd tdati[7] tdati[11] tdati[15] d[2] d[6] a[1] a[5] c d tdat[3] tdat[4] tdat[6] nc tdat[8] tdat[12] vdd d[3] d[7] a[4] d e tfclk tdat[0] tdat[2] tdat[5] e f tadr[0] tadr[1] tadr[2] tdat[1] f g tsoc tprty vdd vdd g h bias tca tenb vdd h j vss nc nc dtca j k vss nc phy_adr[2] vdd bottom view (top left) k 20 19 18 17 16 15 14 13 12 11 quadrant a1/a10 to k1/k10 1098765 4 32 1 a vss vss ale intb trstb tohm/ tneg rclk vss vss vss a b a[9] a[10] wrb tdo tck tclk nc vdd vdd vss b c a[8] csb rstb tms tpos/ tdato rlcv/ rneg/ rohm nc vdd vdd vss c d vdd rdb tdi vdd rpos/ rdati nc bias nc nc vss d e nc vss vss vss e fvssvssncncf gvddncvssvssg h vss toh tohclk vss h j tohins tohfp roh rohfp j k bottom view (top right) rohclk vss vss nc k 109 876 5 4 32 1
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 33 document id: pmc-1990267, issue 3 quadrant l11/l20 to y11/y20 20 19 18 17 16 15 14 13 12 11 l phy_adr[1] phy_adr[0] atmb drca l mnc nc nc rsoc m n vss rca renb radr[1] n p rfclk radr[2] radr[0] vdd p r vdd vdd rprty rdat[13] r t rdat[15] rdat[14] rdat[12] rdat[9] bottom view (bottom left) t u rdat[11] rdat[10] rdat[8] bias rdat[6] rdat[2] vdd tpohclk ref8ko/ rpohfp/ rfpo/ rmfpo vdd u v vss vdd vdd rdat[7] rdat[3] ticlk tpohins rpoh/ rovrhd vss nc v w vss vdd vdd rdat[5] rdat[1] tiohm/ tfpi/ tmfpi tpohfp/ tfpo/ tmfpo/ tgapclk/ tcell rpohclk/ rsclk/ rgapclk vss vss w y vss vss vss rdat[4] rdat[0] tdati/ tpoh lcd/ rdato vss vss vss y 20 19 18 17 16 15 14 13 12 11 quadrant l1/l10 to y1/y10 10987 6 543 21 l vdd nc nc vss l m vss nc nc vss m n nc nc nc vss n p vdd vss nc nc p r nc nc nc vss r t bottom view (bottom right) nc ref8ki nc nc t uncvssncvddncncbiasnc ncfrmstatu vncvssncncvssncncvddvddvssv w nc vss vss nc vss vss nc vdd vdd vss w y nc nc vss nc nc vss nc vss vss vss y 109876543 21
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 34 document id: pmc-1990267, issue 3 9 pin description pin name type pin no. function tpos tdato output c6 the transmit digital positive pulse (tpos) contains the positive pulses transmitted on the b3zs-encoded ds3, hdb3-encoded e3, or b8zs-encoded j2 transmission system when the dual-rail output format is selected. the transmit data (tdato) contains the transmit data stream when the single-rail (unipolar) output format is enabled or when a non-ds3/e3/j2 based transmission system is selected. the tpos/tdato pin function selection is controlled by the tfrm[1:0] and the tuni bits in the s/uni-jet transmit configuration register. output signal polarity control is provided by the tposinv bit in the s/uni-jet transmit configuration register. both tpos and tdato are updated on the falling edge of tclk by default, and may be configured for update on the rising edge of tclk through the tclkinv bit in the s/uni-jet transmit configuration register. also, both tpos and tdato can be updated on the rising edge of ticlk, enabled by the ticlk bit in the s/uni-jet transmit configuration register. tneg tohm output a5 the transmit digital negative pulse (tneg) contains the negative pulses transmitted on the b3zs-encoded ds3, hdb3-encoded e3, or b8zs-encoded j2 transmission system when the dual-rail nrz output format is selected. the transmit overhead mask (tohm) indicates the position of overhead bits (non-payload bits) in the transmission system stream aligned with tdato. tohm indicates the location of the m-frame boundary for ds3, the position of the frame boundary for e3, and the position of the multi-frame boundary for j2 when the single-rail (unipolar) nrz input format is enabled. when a plcp formatted signal is transmitted, tohm is set to logic one once per transmission frame, and indicates the ds1 or e1 frame alignment. when a non-plcp, non-ds3, non-e3, or non-j2 based signal is transmitted, tohm is a delayed version of the tiohm input, and indicates the position of each overhead bit in the transmission frame. tohm is updated on the falling edge of tclk. the tneg/tohm pin function selection is controlled by the tfrm[1:0] and the tuni bits in the s/uni-jet transmit configuration register. output signal polarity control is provided by the tneginv bit in the s/uni-jet transmit configuration register.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 35 document id: pmc-1990267, issue 3 pin name type pin no. function by default, both tneg and tohm are updated on the falling edge of tclk and can be enabled for update on the rising edge of tclk. this sampling is controlled by the tclkinv bit in the s/uni-jet transmit configuration register. also, both tneg and tohm can be updated on the rising edge of ticlk, enabled by the ticlk bit in the s/uni-jet transmit configuration register. tclk output b5 the transmit output clock (tclk) provides the transmit direction timing. tclk is a buffered version of ticlk and can be enabled to update the tpos/tdato and tneg/tohm outputs on its rising or falling edge. rpos rdati input d6 the receive digital positive pulse (rpos) contains the positive pulses received on the b3zs-encoded ds3, the hdb3-encoded e3, or the b8zs-encoded j2 transmission system when the dual-rail nrz input format is selected. the receive data (rdati) contains the data stream when the single-rail (unipolar) nrz input format is enabled or when a non-ds3/e3/j2 based transmission system is being processed (for example, rdati may contain a ds1 or e1 stream). the rpos/rdati pin function selection is controlled by the rfrm[1:0] bits in the s/uni-jet configuration register and by the uni bits in the ds3 frmr, the e3 frmr, or the j2 frmr configuration register. both rpos and rdati are sampled on the rising edge of rclk by default, and may be enabled to be sampled on the falling edge of rclk. this sampling is controlled by the rclkinv bit in the s/uni-jet receive configuration register. note: signal polarity control is provided by the rposinv bit in the s/uni-jet receive configuration register.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 36 document id: pmc-1990267, issue 3 pin name type pin no. function rneg rlcv rohm input c5 the receive digital negative pulse (rneg) contains the negative pulses received on the b3zs encoded ds3, the hdb3-encoded e3, or the b8zs-encoded j2 transmission system when the dual-rail nrz input format is selected. the receive lcv (rlcv) contains lcv indications when the single-rail (unipolar) nrz input format is enabled for ds3, e3, or j2 applications. each lcv is represented by an rclk period-wide pulse. when a ds1 or e1 plcp or atm direct-mapped signal is received, receive overhead mask (rohm) is pulsed once per transmission frame, and indicates the ds1 or e1 frame alignment relative to the rdati data stream. when an alternate frame-based signal is received, rohm indicates the position of each overhead bit in the transmission frame. the rneg/rlcv/rohm pin function selection is controlled by the rfrm[1:0] bits in the s/uni-jet receive configuration register, the uni bits in the ds3 frmr, e3 frmr, or j2 frmr configuration register, and the plcpen and ext bits in the splr configuration register. rneg, rlcv, and rohm are sampled on the rising edge of rclk by default, and may be enabled to be sampled on the falling edge of rclk. this sampling is controlled by the rclkinv bit in the s/uni-jet receive configuration register. note: signal polarity control is provided by the rneginv bit in the s/uni-jet receive configuration register. rclk input a4 the receive clock (rclk) provides the receive direction timing. rclk is the externally recovered transmission system baud rate clock that samples the rpos/rdati and rneg/rlcv/rohm inputs on its rising or falling edge. tohins input j4 the transmit ds3/e3/j2 overhead insertion (tohins) controls the insertion of the ds3, e3, or j2 overhead bits from the toh input. when tohins is high, the associated overhead bit in the toh stream is inserted in the transmitted ds3, e3, or j2 frame. when tohins is low, the ds3, e3, or j2 overhead bit is generated and inserted internally. tohins is sampled on the rising edge of tohclk. if tohins is a logic one, the toh input has precedence over the internal datalink transmitter, or any internal register bit setting.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 37 document id: pmc-1990267, issue 3 pin name type pin no. function toh input h3 when configured for ds3 operation, transmit ds3/e3/j2 overhead data (toh) contains the overhead bits (c, f, x, p, and m) that may be inserted in the transmit ds3 stream. when configured for g.832 e3 operation, toh contains the overhead bytes (fa1, fa2, em mask, tr, ma, nr, and gc) that may be inserted in the transmit g.832 e3 stream. when configured for g.751 e3 operation, toh contains the overhead bits (rai, national use, stuff indication, and stuff opportunity) that may be inserted in the transmit g.751 e3 stream. when configured for j2 operation, toh contains the overhead bits (ts97, ts98, framing, x 1-3 , a, m, e 1-5 ) that may be inserted in the transmit j2 stream. if tohins is a logic one, the toh input has precedence over the internal datalink transmitter, or any other internal register bit setting. toh is sampled on the rising edge of tohclk. tohfp output j3 the transmit ds3/e3/j2 overhead frame position (tohfp) is used to align the individual overhead bits in the transmit overhead data stream, toh, to the ds3 m- frame or the e3 frame. for ds3, tohfp is high during the x1 overhead bit position in the toh stream. for g.832 e3, tohfp is high during the first bit of the fa1 byte. for g.751 e3, tohfp is high during the rai overhead bit position in the toh stream. for j2, tohfp is high during the first bit of timeslot 97 in the first frame of a 4-frame multiframe). tohfp is updated on the falling edge of tohclk. tohclk output h2 the transmit ds3/e3/j2 overhead clock (tohclk) is active when a ds3, e3, or j2 stream is being processed. tohclk is nominally a 526 khz clock for ds3, a 1.072 mhz clock for g.832 e3, a 1.074 mhz clock for g.751 e3, and a gapped 6.312 mhz clock with an average frequency of 168 khz for j2. tohfp is updated on the falling edge of tohclk. toh, and tohins are sampled on the rising edge of tohclk. ref8ki input t3 the plcp frame rate is locked to an external 8 khz reference applied on reference 8 khz input (ref8ki). an internal phase-frequency detector compares the transmit plcp frame rate with the externally applied 8 khz reference and adjusts the plcp frame rate. the ref8ki input must transition high once every 125 s for correct operation. the ref8ki input is treated as an asynchronous signal and must be ?glitch-free?. if the loopt register bit is logic one, the plcp frame rate is locked to the rpohfp signal instead of the ref8ki input.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 38 document id: pmc-1990267, issue 3 pin name type pin no. function tpohins input v14 the transmit path overhead insertion (tpohins) controls the insertion of plcp overhead octets on the tpoh input. when tpohins is logic one, the associated overhead bit in the tpoh stream is inserted in the transmit plcp frame. when tpohins is logic zero, the plcp path overhead bit is generated and inserted internally. tpohins is sampled on the rising edge of tpohclk. note: when operating in g.751 e3 plcp mode, bits 8, 7, and 6 of the c1 octet should not be manipulated. tpoh tdati input y15 the transmit plcp overhead data (tpoh) valid when the frmronly bit in the s/uni-jet configuration 1 register is logic zero. tpoh contains the plcp path overhead octets (zn, f1, b1, g1, m1, m2, and c1) which may be inserted in the transmit plcp frame. the octet data on tpoh is shifted in order from the most significant bit (bit 1) to the least significant bit (bit 8). tpoh is sampled on the rising edge of tpohclk. the framer transmit data (tdati) contains the serial data to be transmitted when the s/uni-jet is configured as a ds3, e3, or j2 framer device for non-atm applications by setting the frmronly bit in the s/uni- jet configuration 1 register. tdati is sampled on the rising edge of ticlk if the txgapen register bit in the s/uni-jet configuration 2 register is logic zero. if txgapen is logic one, then tdati is sampled on the falling edge of tgapclk.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 39 document id: pmc-1990267, issue 3 pin name type pin no. function tpohfp tfpo tmfpo tgapclk output w14 the transmit path overhead frame position (tpohfp) is valid when the frmronly bit in the s/uni-jet configuration 1 register is logic zero. the tpohfp output locates the individual plcp path overhead bits in the transmit overhead data stream, tpoh. tpohfp is logic one while bit 1 (the most significant bit) of the path user channel octet (f1) is present in the tpoh stream. tpohfp is updated on the falling edge of tpohclk. the framer transmit frame pulse/multi-frame pulse reference (tfpo/tmfpo) is valid when the s/uni-jet is configured as a ds3, e3, or j2 framer for non-atm applications by setting the frmronly bit in the s/uni- jet configuration 1 register to logic one and the txgapen bit in the s/uni-jet configuration register to logic zero. tfpo pulses high for 1 out of every 85 clock cycles when configured for ds3, giving a free-running mark for all overhead bits in the frame. tfpo pulses high for 1 out of every 1536 clock cycles when configured for g.751 e3, giving a free-running reference g.751 indication. tfpo pulses high for 1 out of every 4296 clock cycles when configured for g.832 e3, giving a free-running reference g.832 frame indication. tfpo pulses high for 1 out of every 789 clock cycles when configured for j2, giving a free-running reference frame indication. tmfpo pulses high for 1 out of every 4760 clock cycles when configured for ds3, giving a free-running reference m-frame indication. tmfpo pulses high for 1 out of every 3156 clock cycles when configured for j2, giving a free-running reference multi-frame indication. tmfpo behaves the same as tfpo for e3 applications. tfpo and tmfpo are updated on the rising edge of ticlk or rclk if loop-timed. the framer gapped transmit clock (tgapclk) is valid when the s/uni-jet is configured as a ds3, e3, or j2 framer for non-atm applications by setting the frmronly bit in the s/uni-jet configuration 1 register and the txgapen bit in the s/uni-jet configuration 2 register. tgapclk is derived from the transmit reference clock ticlk or from the receive clock if loop-timed. the overhead bit (gapped) positions are generated internal to the device. tgapclk is held high during the overhead bit positions. this clock is useful for interfacing to devices which source payload data only. tgapclk is used to sample tdati.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 40 document id: pmc-1990267, issue 3 pin name type pin no. function tcell the transmit cell indication (tcell) is valid when the tcell bit in the s/uni-jet miscellaneous register is set. tcell pulses once for every cell (idle or assigned) transmitted. tcell is updated using timing derived from the transmit input clock (ticlk), and is active for a minimum of 8 ticlk periods (or 8 rclk periods if loop- timed). tpohclk output u13 the transmit plcp overhead clock (tpohclk) is active when plcp processing is enabled. tpohclk is nominally a 26.7 khz clock for a ds1 plcp frame, a 768 khz clock for a ds3 plcp frame, a 33.7 khz clock for an e1 based plcp frame, and a 576 khz clock for an g.751 e3 based plcp frame. tpohfp is updated on the falling edge of tpohclk. tpoh and tpohins are sampled on the rising edge of tpohclk. tiohm tfpi tmfpi input w15 the transmit input overhead mask (tiohm) is valid only if the frmronly bit in the s/uni-jet configuration 1 register is logic zero. tiohm indicates the position of overhead bits when not configured for ds1, ds3, e1, e3, or j2 transmission system streams. tiohm is delayed internally to produce the tohm output. when configured for operation over a ds1, a ds3, an e1, an e3, or a j2 transmission system sublayer, tiohm is not required, and should be set to logic zero. when configured for other transmission systems, tiohm is set to logic one for each overhead bit position. tiohm is set to logic zero if the transmission system does not contain overhead bits. tiohm is sampled on the rising edge of ticlk. the framer transmit frame pulse/multiframe pulse (tfpi/tmfpi) is valid when the s/uni-jet is configured as a ds3, e3, or j2 framer for non-atm applications by setting the frmronly bit in the s/uni-jet configuration 1 register to logic one. tfpi indicates the position of all overhead bits in each ds3 m-subframe, the first bit in each g.751 e3 or g.832 e3 frame, or the first framing bit in each j2 frame. tfpi is not required to pulse at every frame boundary in e3 or j2 modes. tmfpi indicates the position of the first bit in each ds3 m-frame, the first bit in each e3 frame, or the first framing bit in each j2 multiframe. tmfpi is not required to pulse at every multiframe boundary. tfpi/tmfpi is sampled on the rising edge of ticlk.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 41 document id: pmc-1990267, issue 3 pin name type pin no. function ticlk input v15 the transmit input clock (ticlk) provides the transmit direction timing. ticlk is the externally generated transmission system baud rate clock. it is internally buffered to produce the transmit clock output, tclk, and can be enabled to update the tpos/tdato and tneg/tohm outputs on the ticlk rising edge. the ticlk maximum frequency is 52 mhz. rohfp output j1 the receive ds3/e3/j2 overhead frame position (rohfp) locates the individual overhead bits in the received overhead data stream, roh. rohfp is high during the x1 overhead bit position in the roh stream when processing a ds3 stream. rohfp is high during the first bit of the fa1 byte when processing a g.832 e3 stream. rohfp is high during the rai overhead bit position when processing a g.751 e3 stream. rohfp is high during the first bit in timeslot 97 in the first frame of the 4-frame multiframe when processing a j2 stream. rohfp is updated on the falling edge of rohclk. roh output j2 the receive ds3/e3/j2 overhead data (roh) contains the overhead bits (c, f, x, p, and m) extracted from the received ds3 stream. it also contains the overhead bytes (fa1, fa2, em, tr, ma, nr, and gc) extracted from the received g.832 e3 stream, the overhead bits (rai, national use, stuff indication, and stuff opportunity) extracted from the received g.751 e3 stream, and the overhead bits (framing, x 1-3 , a, m, e 1-5 ) extracted from the received j2 stream. roh is updated on the falling edge of rohclk. rohclk output k4 the receive ds3/e3/j2 overhead clock (rohclk) is active when a ds3, e3, or j2 stream is being processed. rohclk is nominally a 526 khz clock when processing ds3, a 1.072 mhz clock when processing g.832 e3, a 1.074 mhz clock when processing g.751 e3, and a gapped 6.312 mhz clock with an average frequency of 168 khz for j2. roh and rohfp are updated on the falling edge of rohclk.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 42 document id: pmc-1990267, issue 3 pin name type pin no. function ref8ko rpohfp rfpo rmfpo output u12 the reference 8khz output (ref8ko) is an 8khz reference derived from the receive clock (rclk). a free- running divide-down counter is used to generate ref8ko so it will not ?glitch? on reframe actions. ref8ko will pulse high for approximately one rclk cycle every 125 s. ref8ko should be treated as a ?glitch-free? asynchronous signal. the receive plcp overhead frame position (rpohfp) locates the individual plcp path overhead bits in the receive overhead data stream, rpoh. rpohfp is logic one while bit 1 (the most significant bit) of the path user channel octet (f1) is present in the rpoh stream. rpohfp is updated on the falling edge of rpohclk. rpohfp is available when the plcpen register bit is logic one in the splr configuration register. the framer receive frame pulse/multi-frame pulse (rfpo/rmfpo) is valid when the s/uni-jet is configured to be in framer only mode. the 8krefo bit must be set to logic zero in the s/uni-jet configuration register. rfpo is aligned to rdato and indicates the position of the first bit in each ds3 m-subframe, the first bit in each g.751 e3 or g.832 e3 frame, or the first framing bit in each j2 frame rmfpo is aligned to rdato and indicates the position of the first bit in each ds3 m-frame, the first bit in each g.751 or g.832 e3 multiframe, or the first framing bit in each j2 multiframe. rfpo/rmfpo is updated on either the falling or rising edge of rsclk depending on the setting of the rsclkr bit in the s/uni-jet receive configuration register. rpoh rovrhd output v13 the receive plcp overhead data (rpoh) contains the plcp path overhead octets (zn, f1, b1, g1, m1, m2, and c1) extracted from the received plcp frame when the plcp layer is in-frame. when the plcp layer is in the lof state, rpoh is forced to all ones. the octet data on rpoh is shifted out in order from the most significant bit (bit 1) to the least significant bit (bit 8). rpoh is updated on the falling edge of rpohclk. the framer receive overhead indication (rovrhd) is valid when the s/uni-jet is configured as a ds3, e3, or j2 framer for non-atm applications by setting the frmronly bit in the s/uni-jet configuration 1 register. rovrhd will be high whenever the data on rdato corresponds to an overhead bit position. rovrhd is updated on the either the falling or rising edge of rsclk depending on the setting of the rsclkr bit in the s/uni-jet receive configuration register.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 43 document id: pmc-1990267, issue 3 pin name type pin no. function rpohclk rsclk rgapclk output w13 the receive plcp overhead clock (rpohclk) is active when plcp processing is enabled. the frequency of this signal depends on the selected plcp format. rpohclk is nominally a 26.7 khz clock for a ds1 plcp frame, a 768 khz clock for a ds3 plcp frame, a 33.7 khz clock for an e1 based plcp frame, or a 576 khz clock for a g.751 e3 based plcp frame. rpohfp and rpoh are updated on the falling edge of rpohclk. the framer recovered clock (rsclk) is valid when the s/uni-jet is configured as a ds3, e3, or j2 framer for non-atm applications by setting the frmronly bit in the s/uni-jet configuration register. rsclk is the recovered clock and timing reference for rdato, rfpo/rmfpo, and rovrhd. the framer recovered gapped clock (rgapclk) is valid when the s/uni-jet is configured as a ds3, e3, or j2 framer for non-atm applications by setting the frmronly bit in the s/uni-jet configuration 1 register and the rxgapen bit in the s/uni-jet configuration 2 register. rgapclk is the recovered clock and timing reference for rdato. rgapclk is held high for bit positions which correspond to overhead. lcd rdato output y14 the loss of cell delineation (lcd) is an active high signal which is asserted while the atm cell processor has detected a loss of cell delineation defect. the frmronly bit in the s/uni-jet configuration 1 register must be set to logic zero for lcd to be valid. the framer receive data (rdato) is valid when the s/uni-jet is configured as a ds3, e3, or j2 framer for non-atm applications by setting the frmronly bit in the s/uni-jet configuration 1 register. rdato is the received data aligned to rfpo/rmfpo and rovrhd. rdato is updated on the active edge (as set by the rsclkr register bit) of rsclk or rgapclk. frmstat output u1 framer status (frmstat) is an active high signal that can be configured to show when one of the j2, e3, ds3, or plcp framers have detected certain conditions. the frmstat output can be programmed via the statsel[2:0] bits in the s/uni-jet configuration 2 register to indicate: e3/ds3 lof or j2 extended lof, e3/ds3 oof or j2 lof, plcp lof, plcp oof, ais, los, and ds3 idle. frmstat should be treated as a ?glitch-free? asynchronous signal. atm8 input l18 the atm interface bus width selection (atm8) input pin determines whether the s/uni-jet works with a 8-bit wide interface (rdat[7:0] and tdat[7:0]) or a 16-bit wide interface (rdat[15:0] and tdat[15:0]). if atm8 is set to logic one, then the 8-bit wide interface is chosen. if atm8 is set to logic zero, then the 16-bit wide interface is chosen.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 44 document id: pmc-1990267, issue 3 pin name type pin no. function tdat[15] tdat[14] tdat[13] tdat[12] tdat[11] tdat[10] tdat[9] tdat[8] tdat[7] tdat[6] tdat[5] tdat[4] tdat[3] tdat[2] tdat[1] tdat[0] input c15 a16 b16 d15 c16 a17 b17 d16 c17 d18 e17 d19 d20 e18 f17 e19 the transmit cell data bus (tdat[15:0]) carries the atm cell octets that are written to the transmit fifo. tdat[15:0] is sampled on the rising edge of tfclk and is considered valid only when tenb is simultaneously asserted and the s/uni-jet has been selected via the tadr[2:0] inputs. the s/uni-jet can be configured to operate with an 8- bit wide or 16-bit wide atm data interface via the atm8 input pin. when configured for the 8-bit wide interface, tdat[15:8] are not used and should be tied to ground. tprty input g19 the transmit bus parity (tprty) signal indicates the parity of the tdat[15:0] or tdat[7:0] bus. if configured for the 8-bit bus (via the atm8 input pin), then parity is calculated over tdat[7:0]. if configured for the 16-bit bus, then parity is calculated over tdat[15:0]. a parity error is indicated by a status bit and a maskable interrupt. cells with parity errors are inserted in the transmit stream, so the tprty input may be unused. odd or even parity selection is made using the tptyp register bit. tprty is sampled on the rising edge of tfclk and is considered valid only when tenb is simultaneously asserted and the s/uni-jet has been selected via the tadr[2:0] inputs. tsoc input g20 the transmit start of cell (tsoc) signal marks the start of cell on the tdat bus. when tsoc is high, the first word of the cell structure is present on the tdat bus. it is not necessary for tsoc to be present for each cell. an interrupt may be generated if tsoc is high during any word other than the first word of the cell structure. tsoc is sampled on the rising edge of tfclk and is considered valid only when tenb is simultaneously asserted and the s/uni-jet has been selected via the tadr[2:0] inputs. tenb input h18 the transmit multi-phy write enable (tenb) signal is an active low input which is used along with the tadr[2:0] inputs to initiate writes to the transmit fifo. when sampled low using the rising edge of tfclk, the word on the tdat bus is written into the transmit fifo selected by the tadr[2:0] address bus. when sampled high using the rising edge of tfclk, no write is performed, but the tadr[2:0] address is latched to identify the transmit fifo to be accessed. a complete 53-octet cell must be written to the transmit fifo before it is inserted into the transmit stream. idle cells are inserted when a complete cell is not available.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 45 document id: pmc-1990267, issue 3 pin name type pin no. function tadr[2] tadr[1] tadr[0] input f18 f19 f20 the transmit address (tadr[2:0]) bus is used for device selection and device polling in accordance with the utopia level 2 standard. when tadr[2:0] is set to the same value as the phy_adr[2:0] inputs than the transmit interface of this s/uni-jet is either being selected or polled. note: the null-phy address 7h is an invalid address and cannot be used to select the s/uni-jet. tadr[2:0] is sampled on the rising edge of tfclk. tca output h19 the transmit multi-phy cell available (tca) signal indicates when a cell is available in the transmit fifo for the device selected by tadr[2:0]. when high, tca indicates that the corresponding transmit fifo is not full and a complete cell may be written. when tca goes low, it can be configured to indicate either that the corresponding transmit fifo is near full or that the corresponding transmit fifo is full. tca will transition low on the rising edge of tfclk which samples payload byte 43 (tcalevel0=0) or 47 (tcalevel0=1) for the 8-bit interface (atm8=1), or the rising edge of tfclk which samples payload word 19 (tcalevel0=0) or 23 (tcalevel0=1) for the 16-bit interface (atm8=0) if the device being polled is the same as the selected device. to reduce fifo latency, the fifo depth at which tca indicates "full" can be set to one, two, three, or four cells. note: regardless of what fill level tca is set to indicate "full" at, the transmit cell processor can store four complete cells. tca is tri-stated when either the null-phy address (7h) or an address not matching the address space set by phy_adr[2:0] is latched (by tfclk) from the tadr[2:0] inputs. the polarity of tca (with respect the the description above) is inverted when the tcainv register bit is set to logic one. tfclk input e20 the transmit fifo write clock (tfclk) is used to write atm cells to the four-cell transmit fifos. tfclk cycles at a 52 mhz or lower instantaneous rate.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 46 document id: pmc-1990267, issue 3 pin name type pin no. function dtca output j17 the direct access transmit cell available (dtca) output signals indicate when a cell is available in the transmit fifo. when high, dtca indicates that the corresponding transmit fifo is not full and a complete cell may be written. dtca can be configured to indicate either that the corresponding transmit fifo is near full and can accept no more than four writes or that the corresponding transmit fifo is full. dtca will thus transition low on the rising edge of tfclk which samples payload byte 43 (tcalevel0=0) or 47 (tcalevel0=1) for the 8-bit interface (atm8=1), or the rising edge of tfclk which samples payload word 19 (tcalevel0=0) or 23 (tcalevel0=1) for the 16-bit interface (atm8=0). to reduce fifo latency, the fifo depth at which dtca indicates "full" can be set to one, two, three or four cells. note: regardless of what fill level dtca is set to indicate "full" at, the transmit cell processor can store four complete cells. the polarity of dtca (with respect to the description above) is inverted when the tcainv register bit is set to logic one. the dtca outputs can be used to support utopia direct access mode. rdat[15] rdat[14] rdat[13] rdat[12] rdat[11] rdat[10] rdat[9] rdat[8] rdat[7] rdat[6] rdat[5] rdat[4] rdat[3] rdat[2] rdat[1] rdat[0] output t20 t19 r17 t18 u20 u19 t17 u18 v17 u16 w17 y17 v16 u15 w16 y16 the receive cell data bus (rdat[15:0]) bus carries the atm cell octets that are read from the receive atm fifo selected by radr[2:0]. rdat[15:0] is tri-stated when renb is high. rdat[15:0] is updated on the rising edge of rfclk. the s/uni-jet can be configured to operate with an 8- bit wide or 16-bit wide atm data interface via the atm8 input pin. rdat[15:8] will remain tri-stated if atm8 is set to logic one. rdat[15:0] is tri-stated when either the null-phy address (7h) or an address not matching the address space set by phy_adr[2:0] is latched from the radr[2:0] inputs when renb is high.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 47 document id: pmc-1990267, issue 3 pin name type pin no. function rprty output r18 the receive parity (rprty) signal indicates the parity of the rdat bus. the s/uni-jet can be configured to operate with an 8- bit wide or 16-bit wide atm data interface via the atm8 input pin. in the 8-bit mode, rprty reflects the parity of rdat[7:0]. in the 16-bit mode, rprty reflects the parity of rdat[15:0]. odd or even parity selection is made using the rxptyp register bit. rprty is tri-stated when either the null-phy address (7h) or an address not matching the address space set by phy_adr[2:0] is latched from the radr[2:0] inputs when renb is high. rsoc output m17 the receive start of cell (rsoc) signal marks the start of cell on the rdat bus. rsoc marks the start of the cell on the rdat bus. rsoc is tri-stated when either the null-phy address (7h) or an address not matching the address space set by phy_adr[2:0] is latched from the radr[2:0] inputs when renb is high. renb input n18 the receive multi-phy read enable (renb) signal is used to initiate reads from the receive fifo. when sampled low using the rising edge of rfclk, a byte is read (if one is available) from the receive fifo selected by the radr[2:0] address bus and output on the rdat bus. when sampled high using the rising edge of rfclk, no read is performed and rdat[15:0], rprty, and rsoc are tri-stated, and the address on radr[2:0] is latched to select the device or port for the next atm fifo access. renb must operate in conjunction with rfclk to access the fifos at a high enough rate to prevent fifo overflows. the atm layer device may de-assert renb at anytime it is unable to accept another byte. radr[2] radr[1] radr[0] input p19 n17 p18 the receive address (radr[2:0])] bus is used for device selection and device polling in accordance with the utopia level 2 standard. when radr[2:0] is set to the same value as the phy_adr[2:0] inputs than the receive interface of this s/uni-jet is either being selected or polled. note: the null phy address 7h is an invalid address and cannot be used to select the s/uni-jet. radr[2:0] is sampled on the rising edge of tfclk.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 48 document id: pmc-1990267, issue 3 pin name type pin no. function rca output n19 the receive multi-phy cell available (rca) signal indicates when a cell is available in the receive fifo for the device selected by radr[2:0]. rca can be configured to be de-asserted when either zero or four bytes remain in the selected/addressed fifo. rca will thus transition low on the rising edge of rfclk after payload byte 48 (rcalevel0=1) or 43 (rcalevel0=0) is output for the 8-bit interface (atm8=1), or after payload word 24 (rcalevel0=1) or 19 (rcalevel0=0) is output for the 16-bit interface (atm8=0) if the phy being polled is the same as the selected device. rca is tri-stated when either the null-phy address (7h) or an address not matching the address space set by phy_adr[2:0] is latched (by rfclk) from the radr[2:0] inputs. the polarity of rca (with respect to the description above) is inverted when the rcainv register bit is set to logic one. rfclk input p20 the receive fifo read clock (rfclk) signal is used to read atm cells from the receive fifos. rfclk must cycle at a 52 mhz or lower instantaneous rate, but at a high enough rate to avoid fifo overflows. drca output l17 the direct access receive cell available (drca) output signals indicate when a cell is available in the receive fifo. drca can be configured to be de-asserted when either zero or four bytes remain in the fifo. drca will thus transition low on the rising edge of rfclk after payload byte 48 (rcalevel0=1) or 43 (rcalevel0=0) is output for the 8-bit interface (atm8=1), or after payload word 24 (rcalevel0=1) or 19 (rcalevel0=0) is output for the 16-bit interface (atm8=0). the drca outputs can be used to support utopia direct access mode. phy_adr[2] phy_adr[1] phy_adr[0] input k18 l20 l19 the device identification address (phy_adr[2:0]) inputs represent the address space which this s/uni-jet occupies. when the phy_adr[2:0] inputs match the tadr[2:0] or radr[2:0] inputs, then this s/uni-jet is selected for transmit or receive atm access. note: the null-phy address 7h is an invalid address and will not select the s/uni-jet. the s/uni-jet can be used directly in applications requiring 7 or fewer ports. applications requiring more than 7 ports may require external decoding of the utopia address to avoid bus contention. csb input c9 the active low chip select (csb) signal must be low to enable s/uni-jet register accesses. if csb is not used, (rdb and wrb determine register reads and writes) then it should be tied to an inverted version of rstb.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 49 document id: pmc-1990267, issue 3 pin name type pin no. function wrb input b8 the active low write strobe (wrb) signal is pulsed low to enable a s/uni-jet register write access. the d[7:0] bus is clocked into the addressed register on the rising edge of wrb while csb is low. rdb input d9 the active low read enable (rdb) signal is pulsed low to enable a s/uni-jet register read access. the s/uni- jet drives the d[7:0] bus with the contents of the addressed register while rdb and csb are both low. d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] i/o d12 c13 a14 b14 d13 c14 a15 b15 the bi-directional data bus (d[7:0]) is used during s/uni-jet register read and write accesses. a[10] a[9] a[8] a[7] a[6] a[5] a[4] a[3] a[2] a[1] a[0] input b9 b10 c10 a11 b11 c11 d11 a12 b12 c12 b13 the address bus (a[10:0]) selects specific registers during s/uni-jet register accesses. rstb input c8 the active low reset (rstb) signal is set low to asynchronously reset the s/uni-jet. rstb is a schmitt- trigger input with an integral pull-up resistor. ale input a8 the address latch enable (ale) is active-high and latches the address bus a[10:0] when low. when ale is high, the internal address latches are transparent. it allows the s/uni-jet to interface to a multiplexed address/data bus. ale has an integral pull-up resistor. intb output a7 the active low open-drain interrupt (intb) signal goes low when an unmasked interrupt event is detected on any of the internal interrupt sources. note: the intb will remain low until all active, unmasked interrupt sources are acknowledged at their source. tck input b6 the test clock (tck) signal provides timing for test operations that can be carried out using the ieee p1149.1 test access port. tms input c7 the test mode select (tms) signal controls the test operations that can be carried out using the ieee p1149.1 test access port. tms is sampled on the rising edge of tck. tms has an integral pull up resistor. tdi input d8 the test data input (tdi) signal carries test data into the s/uni-jet via the ieee p1149.1 test access port. tdi is sampled on the rising edge of tck. tdi has an integral pull up resistor.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 50 document id: pmc-1990267, issue 3 pin name type pin no. function tdo output b7 the test data output (tdo) signal carries test data out of the s/uni-jet via the ieee p1149.1 test access port. tdo is updated on the falling edge of tck. tdo is a tri- state output which is inactive except when scanning of data is in progress. trstb input a6 the active low test reset (trstb) signal provides an asynchronous s/uni-jet test access port reset via the ieee p1149.1 test access port. trstb is a schmitt triggered input with an integral pull up resistor. trstb must be asserted during the power up sequence. note: if not used, trstb must be connected to the rstb input. bias input h20 u17 d4 u4 when tied to +5v, the +5v bias (bias) input is used to bias the wells in the input and i/o pads so that the pads can tolerate 5v on their inputs without forward biasing internal esd protection devices. when tied to vdd, the inputs and bi-directional inputs will only tolerate input levels up to vdd. vdd[1] vdd[2] vdd[3] vdd[4] vdd[5] vdd[6] vdd[7] vdd[8] vdd[9] vdd[10] vdd[11] vdd[12] vdd[13] vdd[14] vdd[15] vdd[16] vdd[17] vdd[18] vdd[19] vdd[20] vdd[21] vdd[22] vdd[23] vdd[24] vdd[25] vdd[26] vdd[27] vdd[28] vdd[29] vdd[30] vdd[31] vdd[32] power b2 b3 b18 b19 c2 c3 c18 c19 d7 d10 d14 g4 g17 g18 h17 k17 l4 p4 p17 r19 r20 u7 u11 u14 v2 v3 v18 v19 w2 w3 w18 w19 the dc power pins should be connected to a well- decoupled +3.3v dc supply.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 51 document id: pmc-1990267, issue 3 pin name type pin no. function vss[1] vss[2] vss[3] vss[4] vss[5] vss[6] vss[7] vss[8] vss[9] vss[10] vss[11] vss[12] vss[13] vss[14] vss[15] vss[16] vss[17] vss[18] vss[19] vss[20] vss[21] vss[22] vss[23] vss[24] vss[25] vss[26] vss[27] vss[28] vss[29] vss[30] vss[31] vss[32] vss[33] vss[34] vss[35] vss[36] vss[37] vss[38] vss[39] vss[40] vss[41] vss[42] vss[43] vss[44] vss[45] vss[46] vss[47] vss[48] vss[49] ground a1 a2 a3 a9 a10 a13 a18 a19 a20 b1 b20 c1 c20 d1 e1 e2 e3 f3 f4 g1 g2 h1 h4 j20 k2 k3 k20 l1 m1 m4 n1 n20 p3 r1 u9 v1 v6 v9 v12 v20 w1 w5 w6 w8 w9 w11 w12 w20 y1 the dc ground pins should be connected to gnd.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 52 document id: pmc-1990267, issue 3 pin name type pin no. function vss[50] vss[51] vss[52] vss[53] vss[54] vss[55] vss[56] vss[57] vss[58] vss[59] ground y2 y3 y5 y8 y11 y12 y13 y18 y19 y20 the dc ground pins should be connected to gnd. nc[1] nc[2] nc[3] nc[4] nc[5] nc[6] nc[7] nc[8] nc[9] nc[10] nc[11] nc[12] nc[13] nc[14] nc[15] nc[16] nc[17] nc[18] nc[19] nc[20] nc[21] nc[22] nc[23] nc[24] nc[25] nc[26] nc[27] nc[28] nc[29] nc[30] nc[31] nc[32] nc[33] nc[34] nc[35] nc[36] nc[37] nc[38] nc[39] nc[40] nc[41] nc[42] nc[43] nc[44] no connect b4 c4 d2 d3 d5 d17 e4 f1 f2 g3 j18 j19 k1 k19 l2 l3 m2 m3 m18 m19 m20 n2 n3 n4 p1 p2 r2 r3 r4 t1 t2 t4 u2 u3 u5 u6 u8 u10 v4 v5 v7 v8 v10 v11 these pins are no-connects
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 53 document id: pmc-1990267, issue 3 pin name type pin no. function nc[45] nc[46] nc[47] nc[48] nc[49] nc[50] nc[51] nc[52] no connect w4 w7 w10 y4 y6 y7 y9 y10 these pins are no-connects notes 1. all s/uni-jet inputs and bi-directionals present minimum capacitive loading and operate at ttl logic levels. 2. all s/uni-jet outputs and bi-directionals have at least 3 ma drive capability. the data bus outputs, d[7:0], have 3 ma drive capability. the fifo interface outputs, rdat[15:0], rprty, rca, drca, rsoc, tca, and dtca, have 12 ma drive capability. the outputs tclk, tpos/tdato, tneg/tohm, tpohfp/tfpo/tmfpo/tgapclk, lcd/rdato, rpoh/rovrhd, rpohclk/rsclk/rgapclk, and ref8ko/rpohfp/rfpo/rmfpo have 6 ma drive capability. all other outputs have 3 ma drive capability. 3. inputs rstb, ale, tms, tdi, and trstb have internal pull-up resistors. 4. rstb, trstb, tms, tdi, tck, ref8ki, tfclk, rfclk, ticlk, and rclk are schmitt trigger input pads. 5. the vss [59:1] ground pins are not internally connected together. failure to connect these pins externally may cause malfunction or damage the s/uni-jet. 6. the vdd[32:1] power pins are not internally connected together. failure to connect these pins externally may cause malfunction or damage the device. these power supply connections must all be used and must all connect to a common +3.3 v or ground rail, as appropriate. 7. during power-up and power-down, the voltage on the bias pin must be kept equal to or greater than the voltage on the vdd [32:1] pins, to avoid damage to the device.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 54 document id: pmc-1990267, issue 3 10 functional description the s/uni-jet contains the following blocks: ? ds3, e3, j2 framer ? ds3, e3, j2 transmitter ? rboc bit oriented code detector and xboc bit oriented code detector ? rdlc pmdl receiver and tdpr pmdl transmitter ? pmon performance monitor and cppm cell and plcp performance monitor ? splr plcp layer receiver and splt smds plcp layer transmitter ? atmf atm cell delineator ? prgd pseudo-random sequence generator/detector ? rxcp receive cell processor and txcp transmit cell processor ? rxff receive fifo and txff transmit fifo ? ttb trail trace buffer ? jtag test access port 10.1 ds3 framer the ds3 framer (t3-frmr) block integrates the circuitry required for decoding a b3zs-encoded signal and framing to the resulting ds3 bit stream. this block is directly compatible with the m23 and c-bit parity ds3 applications. the t3-frmr decodes a b3zs-encoded signal and provides indications of lcv (lcv). the b3zs decoding algorithm and the lcv definition can be independently chosen through software. a los defect is also detected for b3zs encoded streams. los is declared when inputs rpos and rneg contain zeros for 175 consecutive rclk cycles. los is removed when the ones density on rpos and/or rneg is greater than 33% for 175 1 rclk cycles. the framing algorithm simultaneously examines five f-bit candidates. when at least one discrepancy has occurred in each candidate, the algorithm examines the next set of five. when a single f-bit candidate remains in a set, the first bit in the supposed m-subframe is examined for the m-frame alignment signal such as, the m-bits, m1, m2, and m3 are following the 010 pattern. if the m-bits are correct for three consecutive m-frames while no discrepancies have occurred in the f-bit, framing is declared and out-of-frame (oof) is removed. during the examination of the m-bits, the x-bits and p-bits are ignored. the algorithm gives a maximum average reframe time of 1.5 ms.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 55 document id: pmc-1990267, issue 3 while the t3-frmr is synchronized to the ds3 m-frame, the f-bit and m-bit positions in the ds3 stream are examined. an oof defect is detected when three f-bit errors out of eight or 16 consecutive f-bits are observed (as selected by the m3o8 bit in the ds3 frmr configuration register), or when one or more m-bit errors are detected in three out of four consecutive m- frames. the m-bit error criteria for oof can be disabled by the mbdis bit in the ds3 framer configuration register. the three out of eight consecutive f-bits oof ratio provides more robust operation, in the presence of a high bit error rate, than the three out of 16 consecutive f-bits ratio. either oof criteria allows an oof defect to be detected quickly when the m-subframe alignment patterns or, optionally, when the m-frame alignment pattern is lost. also while in-frame, lcv, m-bit or f-bit framing bit errors, and p-bit parity errors are indicated. when c-bit parity mode is enabled, both c-bit parity errors and febes are indicated. these error indications, as well as the lcv and excessive zeros indication, are accumulated over one second intervals with the performance monitor (pmon). note: the framer is an off-line framer, indicating both oof and cofa events. even if an oof is indicated, the framer will continue indicating performance monitoring information based on the previous frame alignment. three ds3 maintenance signals (a red alarm condition, the ais, and the idle signal) are detected by the t3-frmr. the maintenance detection algorithm uses a simple integrator with a 1:1 slope that is based on the occurrence of "valid" m-frame intervals. for the red alarm, an m-frame is said to be a "valid" interval if it contains a red defect, defined as an occurrence of an oof or los event during that m-frame. for ais and idle, an m-frame interval is "valid" if it contains ais or idle, defined as the occurrence of less than 15 discrepancies in the expected signal pattern (1010.. for ais, 1100.. for idle) while valid frame alignment is maintained. this discrepancy threshold ensures the detection algorithms operate in the presence of a 10 -3 bit error rate. for ais, the expected pattern may be selected to be: the framed "1010" signal; the framed arbitrary ds3 signal and the c-bits all zero; the framed "1010" signal and the c-bits all zero; the framed all-ones signal (with overhead bits ignored); or the unframed all-ones signal (with overhead bits equal to ones). each "valid" m-frame causes an associated integration counter to increment; "invalid" m-frames cause a decrement. with the "slow" detection option, red, ais, or idle are declared when the respective counter saturates at 127, which results in a detection time of 13.5 ms. with the "fast" detection option, red, ais, or idle are declared when the respective counter saturates at 21, which results in a detection time of 2.23 ms, that is, 1.5 times the maximum average reframe time. red, ais, or idle are removed when the respective counter decrements to zero. ds3 lof detection is provided as recommended by itu-t g.783 with programmable integration periods of 1 ms, 2 ms, or 3 ms. while integrating up to assert lof, the counter will integrate up when the framer asserts an oof condition and integrates down when the framer de-asserts the oof condition. once an lof is asserted, the framer must not assert oof for the entire integration period before lof is de-asserted.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 56 document id: pmc-1990267, issue 3 valid x-bits are extracted by the t3-frmr to provide indication of far end receive failure (ferf). a ferf defect is detected if the extracted x-bits are equal and are logic zero (x1=x2=0); the defect is removed if the extracted x-bits are equal and are logic one (x1=x2=1). if the x-bits are not equal, the ferf status remains in its previous state. the extracted ferf status is buffered for two m-frames before being reported within the ds3 frmr status register. this buffer ensures a better than 99.99% chance of freezing the ferf status on a correct value during the occurrence of an oof. when the c-bit parity application is enabled, both the feac channel and the pmdl are extracted. codes in the feac channel are detected by the bit oriented code detector (rboc). hdlc messages in the pmdl are received by the data link receiver (rdlc). the t3-frmr can be enabled to automatically assert the rai indication in the outgoing transmit stream upon detection of any combination of los, oof or red, or ais. the t3-frmr can also be enabled to automatically insert c-bit parity febe upon detection of receive c-bit parity error. the t3-frmr extracts the entire ds3 overhead (56 bits per m-frame) using the roh output, along with the rohclk, and rohfp outputs. the t3-frmr may be configured to generate interrupts on error events or status changes. all sources of interrupts can be masked or acknowledged via internal registers. internal registers are also used to configure the t3-frmr. access to these registers is via a generic microprocessor bus. 10.2 e3 framer the e3 framer (e3-frmr) block integrates circuitry required for decoding an hdb3-encoded signal and framing to the resulting e3 bit stream. the e3-frmr is directly compatible with the g.751 and g.832 e3 applications. the e3-frmr searches for frame alignment in the incoming serial stream based on either the g.751 or g.832 formats. for the g.751 format, the e3-frmr expects to see the selected framing pattern error-free for three consecutive frames before declaring inframe. for the g.832 format, the e3-frmr expects to see the selected framing pattern error-free for two consecutive frames before declaring inframe. once the frame alignment is established, the incoming data is continuously monitored for framing bit errors and byte interleaved parity errors (in g.832 format). while in-frame, the e3-frmr also extracts various overhead bytes and processes them according to the framing format selected: in g.832 e3 format, the e3-frmr extracts: ? the trail trace bytes and outputs them as a serial stream for further processing by the trail trace buffer (ttb) block. ? the ferf bit and indicates an alarm when the ferf bit is a logic one for three or five consecutive frames. the ferf indication is removed when the ferf bit is a logic zero for three or five consecutive frames. ? the febe bit and outputs it for accumulation in pmon.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 57 document id: pmc-1990267, issue 3 ? the payload type bits and buffers them so that they can be read by the microprocessor. ? the timing marker bit and asserts the timing marker indication when the value of the extracted bit has been in the same state for three or five consecutive frames. ? the network operator byte and presents it as a serial stream for further processing by the rdlc block when the rnetop bit in the s/uni-jet data link and ferf control register is logic one. the byte is also brought out on the roh[x] output with an associated clock on rohclk[x]. all eight bits of the network operator byte are extracted and presented on the overhead output and, optionally, presented to the rdlc. ? the general purpose communication channel byte and presents it to the rdlc when the rnetop bit in the s/uni-jet data link and ferf control register is logic zero the byte is also brought out on the roh[x] output with an associated clock on rohclk[x]. in g.751 e3 mode, the e3-frmr extracts: ? the rai bit (bit 11 of the frame) and indicates a remote alarm when the rai bit is a logic one for three or five consecutive frames. similarly, the remote alarm is removed when the rai bit is logic zero for three or five consecutive frames. ? the national use reserved bit (bit 12 of the frame) and presents it as a serial stream for further processing in the rdlc when the rnetop bit in the s/uni-jet data link and ferf control register is logic zero. the bit is also brought out on the roh[x] output with an associated clock on rohclk[x]. optionally, an interrupt can be generated when the national use bit changes state. further, while in-frame, the e3-frmr indicates the position of all the overhead bits in the incoming digital stream to the atmf/splr block. for g.751 mode, the tributary justification bits can be optionally identified as either overhead or payload for payload mappings that take advantage of the full bandwidth. the e3-frmr declares oof alignment if the framing pattern is in error for four consecutive frames. the e3-frmr is an "off-line" framer, where all frame alignment indications, all overhead bit indications, and all overhead bit processing continue based on the previous alignment. once the framer has determined the new frame alignment, the oof indication is removed and a cofa indication is declared if the new alignment differs from the previous alignment. the e3-frmr detects the presence of ais in the incoming data stream when less than eight zeros in a frame are detected while the framer is oof in g.832 mode, or when less than five zeros in a frame are detected while oof in g.751 mode. this algorithm provides a probability of detecting ais in the presence of a 10 -3 ber as 92.9% in g.832 and 98.0% in g.751. los is declared when no marks have been received for 32 consecutive bit periods. los de- asserted after 32 bit periods during which there is no sequence of four consecutive zeros.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 58 document id: pmc-1990267, issue 3 e3 lof detection is provided as recommended by itu-t g.783 with programmable integration periods of 1 ms, 2 ms, or 3 ms. while integrating up to assert lof, the counter will integrate up when the framer asserts an oof condition and integrates down when the framer de-asserts the oof condition. once an lof is asserted, the framer must not assert oof for the entire integration period before lof is de-asserted. the e3-frmr can also be enabled to automatically assert the rai/ferf indication in the outgoing transmit stream upon detection of any combination of los, oof or ais. the e3-frmr can also be enabled to automatically insert g.832 febe upon detection of receive bip-8 errors. 10.3 j2 framer the j2-frmr integrates circuitry to decode a unipolar or b8zs encoded signal and frame to the resulting 6312 kbps j2 bit stream. having found frame, the j2-frmr extracts a variety of overhead and datalink information from the j2 bit stream. the j2 format consists of 789-bit frames, each 125 s long, consisting of 96 bytes of payload, 2 reserved bytes, and five f-bits. the frames are grouped into 4-frame multiframes. the multiframe format is described in table 4. table 4 multiframe format bit # 1-8 .. 761-768 769-776 777-784 785 786 787 788 789 1 ts1[1:8] .. ts96[1:8] ts97[1:8] ts98[1:8] 1 1 0 0 m 2 ts1[1:8] .. ts96[1:8] ts97[1:8] ts98[1:8] 1 0 1 0 0 3 ts1[1:8] .. ts96[1:8] ts97[1:8] ts98[1:8] x1 x2 x3 a m 4 ts1[1:8] .. ts96[1:8] ts97[1:8] ts98[1:8] e1 e2 e3 e4 e5 notes 1. ts1 . ts96 are the byte interleaved payloads. 8. ts97 , ts98 are reserved channels for signaling. 9. the frame alignment signal is represented as binary ones and zeroes. 10. m is a 4-khz datalink. 11. x1 , x2 , and x3 are spare bits, usually logic one. 12. a is the remote lof alarm bit, active high. 13. e1 . e5 represent the crc-5 check sequence. the entire 3156-bit multiframe, including the crc-5 check sequence, should have a remainder of 0 when divided by x 5 + x 4 + x 2 + 1.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 59 document id: pmc-1990267, issue 3 the j2-frmr frames to a j2 signal with an average reframe time of 5.07 ms. an alternate framing algorithm that uses the crc-5 check to detect static mimic patterns is also available. once in frame, the j2-frmr provides indications of frame and multiframe boundaries, and marks overhead bits, x-bits, m-bits, and reserved channels (ts97 and ts98). indications of los, bipolar violations, excessive zeroes, change of frame alignment, framing errors, and crc errors are provided, and may be accumulated by the pmon (with the exception of change of frame alignment). maskable interrupts are available to alert the microprocessor to the occurrence of any of these events. in addition to marking x-bit values, j2-frmr provides microprocessor access to the x-bits, and will optionally generate an interrupt when any of the x-bits change state. the m- bits and the associated clock are can either be extracted through the rdlc or through the roh[x] and rohclk[x] output pins of the s/uni-jet . the m-bits are also presented to the rboc for detection of any generic bit-oriented codes. the j2-frmr detects status signals such as physical ais, payload ais, rai in m-bits, and remote lof (a-bit). it also optionally generates an interrupt when any of these status signals change. j2 los is declared when no marks have been received for one of 15, 31, 63, or 255 consecutive bit periods. j2 los is cleared when either 15, 31, 63, or 255 consecutive bit periods have passed without detection of excessive zeros (meaning eight or more consecutive zeros) as required by itu-t g.775. j2 lof is declared when seven or more consecutive multiframes with errored framing patterns are received. the j2 lof is cleared when three or more consecutive multiframes with correct framing patterns are received. also available are framing algorithms that take into account the crc calculation. these framing algorithms are described in the following section. j2 physical layer ais is declared when two or less zeros are detected in a sequence of 3156 bits. it is cleared when three or more zeros is detected in a sequence of 3156 bits as required by itu-t g.775. j2 payload ais is detected when the incoming j2 payload has two or less zeros in a sequence of 3072 bits. it is cleared when three or more zeros are detected in a sequence of 3072 bits. note: the j2-frmr may be forced to re-frame by microprocessor control. similarly, the microprocessor may disable the j2-frmr from reframing due to framing bit errors. you can configure the j2-frmr and mask or acknowledge all sources of interrupts through the internal registers. these internal registers are accessed from a generic microprocessor bus. 10.3.1 j2 frame find algorithms the j2-frmr searches for frame alignment using one of two algorithms, as selected by the crc_refr bit in the j2-frmr configuration register.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 60 document id: pmc-1990267, issue 3 when the crc_refr bit is set to logic zero, the j2-frmr uses only the frame alignment sequence to find frame, searching for three consecutive correct frame alignment sequences. the frame find block searches for the entire 9-bit sequence (spread over two multiframes) at the same time, greatly reducing the time required to find frame alignment. the framing process with crc- refr cleared is illustrated in figure 4. figure 4 framing algorithm (crc_refr = 0) mark multifram e alignm ent confirm framing pattern in next multiframe slip 1 bit framing pattern matched reset or out of frame else fail confirm framing pattern in next m ultifram e fail pass declare in-frame pass using this algorithm, the j2-frmr will on average find frame in 5.07 ms when starting the search in the worst possible position, given a 10 - 4 error rate and no static mimic patterns. when the crc_refr bit is set to logic one, in addition to requiring three consecutive correct framing patterns, the j2-frmr requires that the first two crc-5 checks be correct, or a reframe is initiated. to speed up the process, the crc-5 and frame alignment checks are run concurrently, as illustrated in figure 5.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 61 document id: pmc-1990267, issue 3 figure 5 framing algorithm (crc_refr = 1) mark multifram e alignm ent confirm framing pattern in next m ultifram e slip 1 bit framing pattern matched else fail confirm framing pattern in next m ultifram e pass declare in-frame pass check crc-5 sequence pass pass check crc-5 sequence fail reset or out of frame fail fail using this algorithm, the j2-frmr will find frame in 10.22 ms, on average when starting the search in the worst possible position, given a 10 -4 error rate and no static mimic patterns. the algorithm will reject 99.90% of mimic patterns. further protection against mimic patterns is available by monitoring the rate of crc-5 errors. once frame alignment is found, the block sets the lof indication low, indicates a change of frame alignment (if it occurred). the block declares lof alignment if 7 consecutive fass have been received in error. in the presence of a random 10 - 3 bit error rate the frame loss criteria provides a mean time to falsely lose frame alignment of 1.65 years. the frame find block can be forced to initiate a frame search at any time when the reframe bit in the j2-frmr configuration. conversely, when the flock bit is set to logic one, the j2-frmr will never declare lof or search for a new frame alignment due to excess framing bit errors.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 62 document id: pmc-1990267, issue 3 j2 extended lof detection is provided as recommended by itu-t g.783 with programmable integration periods of 1 ms, 2 ms, or 3 ms. while integrating up to assert lof, the counter will integrate up when the framer asserts an oof condition and integrates down when the framer de- asserts the oof condition. once an lof is asserted, the framer must not assert oof for the entire integration period before lof is de-asserted. 10.4 rboc bit-oriented code detector note: the bit-oriented code detector is only used in ds3 c-bit parity or j2 mode. the bit-oriented code detector (rboc) block detects the presence of 63 of the 64 possible bit- oriented codes (bocs) contained in the ds3 c-bit parity far-end alarm and control (feac) channel or in the j2 datalink signal stream. the 64 th code ("111111") is similar to the hdlc flag sequence and is ignored. bocs are received on the feac channel as 16-bit sequences each consisting of eight ones, a zero, six code bits, and a trailing zero ("111111110xxxxxx0"). bocs are validated when repeated at least 10 times. the rboc can be enabled to declare a code valid if it has been observed for eight out of 10 times or for four out of five times, as specified by the avc bit in the rboc configuration/interrupt enable register. the rboc declares that the code is removed if two code sequences containing code values that are different from the detected code are received in a moving window of 10 code periods. valid bocs are indicated through the rboc interrupt status register. the boc bits are set to all-ones ("111111") when no valid code is detected. the rboc can be programmed to generate an interrupt when a detected code has been validated and when the code is removed. 10.5 rdlc pmdl receiver the rdlc is a microprocessor peripheral used to receive lapd/hdlc frames on any serial hdlc bit stream that provides data and clock information such as the ds3 c-bit parity path maintenance data link, the e3 g.832 network requirement byte or the general purpose data link (selectable using the rnetop bit in the s/uni-jet data link and ferf/rai control register), the e3 g.751 network use bit, or the j2 m-bit data link. the rdlc detects the change from flag characters to the first byte of data, removes stuffed zeros on the incoming data stream, receives packet data, and calculates the crc-ccitt frame check sequence (fcs). in the address matching mode, only those packets whose first data byte matches one of two programmable bytes or the universal address (all ones) are stored in the fifo. the two least significant bits of the address comparison can be masked for lapd sapi matching. received data is placed into a 128-level fifo buffer. an interrupt is generated when a programmable number of bytes are stored in the fifo buffer. other sources of interrupt are detection of the terminating flag sequence, abort sequence, or fifo buffer overrun.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 63 document id: pmc-1990267, issue 3 the status register contains bits that indicate the overrun or empty fifo status, the interrupt status, and the occurrence of first flag or end of message bytes written into the fifo. the status register also indicates the abort, flag, and end-of-message status of the data just read from the fifo. on end of message, the status register indicates the fcs status and if the packet contained a non-integer number of bytes. 10.6 pmon performance monitor accumulator the pmon block interfaces directly with either the ds3 framer (t3-frmr) to accumulate lcv events, parity error (perr) events, path parity error (cperr) events, febe events, excess zeros (exzs), and framing bit error (ferr) events using the saturating counters: ? the e3 framer (e3-frmr) to accumulate lcv, perr (in g.832 mode), febe and ferr events, or ? the j2 framer (j2-frmr) to accumulate lcvs, crc errors (in the perr counter), framing bit errors (ferr), and excess zeros (exzs). the pmon stops accumulating error signals from the e3, ds3, or j2 framers once frame synchronization is lost. when an accumulation interval is signaled by a write to the pmon register address space or a write to the s/uni-jet identification, master reset, and global monitor update register, the pmon transfers the current counter values into microprocessor-accessible holding registers and resets the counters to begin collecting error events for the next interval. the counters are reset in such a manner that error events occurring during the reset period are not missed. when counter data is transferred into the holding registers, an interrupt will be generated if it has been enabled. if the holding registers have not been read since the last interrupt, an overrun status bit is set. also provided is a register to indicate changes in the pmon counters since the last accumulation interval. 10.7 splr plcp layer receiver the plcp layer receiver (splr) block integrates circuitry to support ds1, ds3, e1, and g.751 e3 plcp frame processing. the splr provides framing for plcp based transmission formats. the splr frames to ds1, ds3, e1, and g.751 e3 based plcp frames with maximum average reframe times of 635 s, 22 s, 483 s, and 32 s respectively. framing is declared (oof is removed) upon finding two valid, consecutive sets of framing (a1 and a2) octets and two valid and sequential path overhead identifier (pohid) octets. while framed, the a1, a2, and pohid octets are examined. oof is declared when an error is detected in both the a1 and a2 octets or when two consecutive pohid octets are found in error. lof is declared when an oof state persists for more than 25 ms, 1 ms, 20 ms, or 1 ms for ds1, ds3, e1, or g.751 e3 plcp formats respectively. if the oof events are intermittent, the lof counter is decremented at a rate 1/12 (ds3 plcp), 1/10 (e1, ds1 plcp) or 1/9(g.751 e3 plcp) of the incrementing rate. lof is thus removed when an in-frame state persists for more than 250 ms for a ds1 signal, 12 ms for a ds3 signal, 200 ms for an e1 signal, or 9 ms for a g.751 e3 signal. when lof is declared, plcp reframe is initiated.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 64 document id: pmc-1990267, issue 3 when in frame, the splr extracts the path overhead octets and outputs them bit serially on output rpoh, along with the rpohclk and rpohfp outputs. framing octet errors and path overhead identifier octet errors are indicated as frame errors. bit interleaved parity errors and febes are indicated. the yellow signal bit is extracted and accumulated to indicate yellow alarms. yellow alarms are declared when 10 consecutive yellow signal bits are set to logic one. it is removed when 10 consecutive received yellow signal bits are set to logic zero. the c1 octet is examined to maintain nibble alignment with the incoming transmission system sublayer bit stream. 10.8 atmf atm cell delineator the atm cell delineator (atmf) block integrates circuitry to support hcs-based cell delineation for non-plcp based transmission formats. the atmf block accepts a bit serial cell stream from an upstream transmission system sublayer entity (such as the t3-frmr, e3-frmr, or j2-frmr block) and performs cell delineation to locate the cell boundaries. for plcp applications, atm cell positions are fixed relative to the plcp frame, but the atmf still performs cell delineation to locate the cell boundaries. cell delineation is the process of framing to atm cell boundaries using the hcs field found in the atm cell header. the hcs is a crc-8 calculation over the first four octets of the atm cell header. when performing delineation, correct hcs calculations are assumed to indicate cell boundaries. the atmf performs a sequential bit-by-bit, a nibble-by-nibble (ds-3 direct mapped), or a byte- by-byte (j2 and e3 direct-mapped) hunt for a correct hcs sequence. this state is referred to as the hunt state. when receiving a bit serial cell stream from an upstream transmission-system sublayer entity, the bit, nibble, or byte boundaries are determined from the location of the overhead. when a correct hcs is found, the atmf locks on the particular cell boundary and assumes the presync state. this state verifies that the previously detected hcs pattern was not a false indication. if the hcs pattern was a false indication then an incorrect hcs should be received within the next delta cells. at that point a transition back to the hunt state is executed. if an incorrect hcs is not found in this presync period then a transition to the sync state is made. in this state synchronization is not relinquished until alpha consecutive incorrect hcs patterns are found. in such an event a transition is made back to the hunt state. the state diagram of the cell delineation process is shown in figure 6.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 65 document id: pmc-1990267, issue 3 figure 6 cell delineation state diagram hunt presync sync correct hcs (bit by bit) incorrect hcs (cell by cell) delta consecutive correct hcs's (cell by cell) alpha consecutive incorrect hcs's (cell by cell) the values of alpha and delta determine the robustness of the delineation method. alpha determines the robustness against false misalignments due to bit errors. delta determines the robustness against false delineation in the synchronization process. alpha is chosen to be 7 and delta is chosen to be 6 as recommended in itu-t recommendation i.432. these values result in a maximum average time to frame of 127 s for a ds3 stream carrying atm cells directly mapped into the ds3 information payload. lcd is detected by counting the number of incorrect cells while in the hunt state. the counter value is stored in the rxcp-50 lcd count threshold register. the threshold has a default value of 360 which results in: ? a ds3 application detection time of 3.5 ms. ? an e3 g.832 application detection time of 4.5 ms. ? an e3 g.751 application detection time of 5.0 ms. ? a j2 application time of 24.8ms, an e1 application detection time of 77 ms. ? a ds1 application detection time of 100 ms. if the counter value is set to zero, the lcd output signal is asserted for every incorrect cell. 10.9 prgd pseudo-random sequence generator/detector the pseudo-random sequence generator/detector (prgd) block is a software programmable test pattern generator, receiver, and analyzer. two types of test patterns (pseudo-random and repetitive) conform to itu-t o.151.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 66 document id: pmc-1990267, issue 3 the prgd can be programmed to generate any pseudo-random pattern with length up to 2 32 -1 bits or any user programmable bit pattern from 1 to 32 bits in length. the prgd can also insert single bit errors or a bit error rate between 10 -1 to 10 -7 . the prgd can be programmed to check for the presence of the generated pseudo-random pattern. the prgd can perform an auto-synchronization to the expected pattern, and generate interrupts on detection and loss of the specified pattern. the prgd can accumulate the total number of bits received and the total number of bit errors in two saturating 32-bit counters. the counters accumulate over an interval defined by writes to the s/uni-jet identification/master reset, and global monitor update register (006h) or by writes to any prgd accumulation register. when an accumulation is forced by either method, then the holding registers are updated, and the counters reset to begin accumulating for the next interval. the counters are reset in such a way that no events are missed. the data is then available in the holding registers until the next accumulation. in addition to the two counters, a record of the 32 bits received immediately prior to the accumulation is available. the prgd may also be programmed to check for repetitive sequences. when configured to detect a pattern of length n bits, the prgd will load n bits from the detected stream, and determine whether the received pattern repeats itself every n subsequent bits. should it fail to find such a pattern, it will continue loading and checking until it finds a repetitive pattern. all the features (error counting, auto-synchronization, etc.) available for pseudo-random sequences are also available for repetitive sequences. whenever a prgd accumulation is forced, the prgd stores a snapshot of the 32 bits received immediately prior to the accumulation. this snapshot may be examined in order to determine the exact nature of the repetitive pattern received by prgd. the pseudo-random or repetitive pattern can be inserted/extracted in the plcp payload (if plcp framing is enabled) or in the ds3, e3, j2, or arbitrary framing format payload (if plcp framing is disabled). it cannot be inserted into the atm cell payload. 10.10 rxcp-50 receive cell processor the receive cell processor (rxcp-50) block integrates circuitry to support: ? scrambled or unscrambled cell payloads. ? scrambled or unscrambled cell headers. ? hcs verification. ? idle cell filtering. ? performance monitoring. the rxcp-50 operates upon a delineated cell stream. for plcp based transmissions systems, cell delineation is performed by the splr. for non-plcp based transmission systems, cell delineation is performed by the atmf. framing status indications from these blocks ensure that cells are not written to the rxff while the splr is in the lof state, or cells are not written to the rxff while the atmf is in the hunt or presync states.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 67 document id: pmc-1990267, issue 3 the rxcp-50 descrambles the cell payload field using the self synchronizing descrambler with a polynomial of x 43 + 1. the header portion of the cells can optionally be descrambled also. note: cell payload scrambling is enabled by default in the s/uni-jet as required by itu-t recommendation i.432, but may be disabled to ensure backwards compatibility with older equipment. the hcs is a crc-8 calculation over the first four octets of the atm cell header. the rxcp-50 verifies the received hcs using the accumulation polynomial, x 8 + x 2 + x + 1. the coset polynomial x 6 + x 4 + x 2 + 1 is added (modulo 2) to the received hcs octet before comparison with the calculated result as required by the atm forum uni specification, and itu-t recommendation i.432. the rxcp-50 can be programmed to drop all cells containing an hcs error or to filter cells based on the hcs and the cell header. filtering according to a particular hcs and the gfc, pti, and clp bits of the atm cell header is programmable through the rxcp-50 registers. note: the vci and vpi bits must be all logic zero. more precisely, filtering is performed when filtering is enabled or when hcs errors are found when hcs checking is enabled. otherwise, all cells are passed on regardless of any error conditions. cells can be blocked if the hcs pattern is invalid or if the filtering 'match pattern' and 'match mask' registers are programmed with a certain blocking pattern. atm idle cells are filtered by default. for atm cells, null or idle cells are identified by the standardized header pattern of 'h00, 'h00, 'h00 and 'h01 in the first four octets followed by the valid hcs octet. while the cell delineation state machine is in the sync state, the hcs verification circuit implements the state machine shown in figure 7.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 68 document id: pmc-1990267, issue 3 figure 7 hcs verification state diagram detection mode atm delineation sync state correction mode no errors detected in m (m = 1, 2, 4, or 8) consecutive cells (pass last cell) apparent multi-bit error (drop cell) no errors detected (pass cell) alpha consecutive incorrect hcs's (to hunt state) delta consecutive correct hcs's (from presync state) single bit error (correct error and pass cell) drop cell in normal operation, the hcs verification state machine remains in the 'correction' state. incoming cells containing no hcs errors are passed to the receive fifo. incoming single-bit errors are corrected, and the resulting cell is passed to the fifo. upon detection of a single-bit error or a multi-bit error, the state machine transitions to the 'detection' state. a programmable hysteresis is provided when dropping cells based on hcs errors. when a cell with an hcs error is detected, the rxcp-50 can be programmed to continue to discard cells until m (where m = 1, 2, 4, 8) cells are received with a correct hcs. the mth cell is not discarded (see figure 7). note: the dropping of cells due to hcs errors only occurs while the atmf is in the sync state. cell delineation can optionally be disabled, allowing the rxcp-50 to pass all data bytes it receives. 10.11 rxff receive fifo the receive fifo (rxff) provides fifo management and the s/uni-jet receive cell interface. the receive fifo contains four cells. the fifo provides the cell rate decoupling function between the transmission system physical layer and the atm layer. the general management functions of the rxff are:
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 69 document id: pmc-1990267, issue 3 ? filling the receive fifo. ? indicating when the receive fifo contains cells. ? maintaining the receive fifo read and write pointers. ? detecting fifo overrun and underrun conditions. the fifo interface is ?utopia level 2"-compliant. it accepts a read clock (rfclk) and read enable signal (renb). the receive fifo output bus (rdat[15:0]) is tri-stated when renb is logic one or if the phy device address (radr[4:0]) selected does not match this device's address. the interface indicates the start of a cell (rsoc) and the receive cell available status (rca and drca[4:1]) when data is read from the receive fifo (using the rising edges of rfclk). the rca (and drca[x]) status changes from available to unavailable when the fifo is either empty (rcalevel0=1) or near empty (rcalevel0 is logic zero). the interface also indicates fifo overruns via a maskable interrupt and register bits. read accesses while rca (or drca[x]) is a logic zero will output invalid data. 10.12 cppm cell and plcp performance monitor the cell and plcp performance monitor (cppm) block interfaces directly to the splr to accumulate bit interleaved parity error events, framing octet error events, and febe events in saturating counters. when the plcp framer (splr) declares lof, the following are not counted: bit interleaved parity error events, framing octet error events, febe events, hcs error events. when an accumulation interval is signaled by a write to the cppm register address space or to the s/uni-jet identification, master reset, and global monitor update register, the cppm transfers the current counter values into holding registers and resets the counters to begin accumulating error events for the next interval. the counters are reset in such a manner that error events occurring during the reset period are not missed. 10.13 ds3 transmitter the ds3 transmitter (t3-tran) block integrates circuitry required to insert the overhead bits into a ds3 bit stream and produce a b3zs-encoded signal. the t3-tran is directly compatible with the m23 and c-bit parity ds3 formats. status signals such as far end receive failure (ferf), the ais, and the idle signal can be inserted when their transmission is enabled by internal register bits. ferf can also be automatically inserted on detection of any combination of los, oof or red, or ais by the t3-frmr. a valid pair of p-bits is automatically calculated and inserted by the t3-tran. when c-bit parity mode is selected, the path parity bits, and febe indications are automatically inserted. when enabled for c-bit parity operation, the feac channel is sourced by the xboc bit-oriented code transmitter. the pmdlmessages are sourced by the tdpr data link transmitter. these overhead signals can also be overwritten by using the toh[x] and tohins[x] inputs.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 70 document id: pmc-1990267, issue 3 when enabled for m23 operation, the c-bits are forced to logic one with the exception of the c- bit parity id bit (first c-bit of the first m-subframe), which is forced to toggle every m-frame. the t3-tran supports diagnostic modes in which it inserts parity or path parity errors, f-bit framing errors, m-bit framing errors, invalid x or p-bits, lcv, or all-zeros. user control of each of the overhead bits in the ds3 frame is provided. overhead bits may be inserted on a bit-by-bit basis from a user supplied data stream. an overhead clock (at 526 khz) and a ds3 overhead alignment output are provided to allow for control of the user provided stream. 10.14 e3 transmitter the e3 transmitter (e3-tran) block integrates circuitry required to insert the overhead bits into an e3 bit stream and produce an hdb3-encoded signal. the e3-tran is directly compatible with the g.751 and g.832 framing formats. the e3-tran generates the frame alignment signal and inserts it into the incoming serial stream based on either the g.751 or g.832 formats and an alignment pulse applied to it by the splt block. all overhead and status bits in each frame format can be individually controlled by register bits or by the transmit overhead stream. while in certain framing format modes, the e3-tran generates various overhead bytes according to the following format or mode. in g.832 e3 format, the e3-tran: ? inserts the bip-8 byte calculated over the preceding frame. ? inserts the trail trace bytes through the trail trace buffer (ttb) block. ? inserts the ferf bit via a register bit or, optionally, when the e3-frmr declares oof, or when the loss of cell delineation (lcd) defect is declared. ? inserts the febe bit, which is set to logic one when one or more bip-8 errors are detected by the receive framer. if there are no bip-8 errors indicated by the e3-frmr, the e3-tran sets the febe bit to logic zero. ? inserts the payload type bits based on the register value set by the microprocessor. ? inserts the tributary unit multiframe indicator bits either via the toh overhead stream or by register bit values set by the microprocessor. ? inserts the timing marker bit via a register bit. ? inserts the network operator (nr) byte from the tdpr block when the tnetop bit in the s/uni-jet data link and ferf control register is logic one; otherwise, the nr byte is set to all ones. the nr byte can be overwritten by using the toh[x] and tohins[x] input pins. all eight bits of the network operator byte are available for use as a datalink. ? inserts the general purpose communication channel (gc) byte from the tdpr block when the tnetop bit in the s/uni-jet data link and ferf control register is logic zero; otherwise, the byte is set to all ones. the gc byte can be overwritten by using the toh[x] and tohins[x] input pins.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 71 document id: pmc-1990267, issue 3 in g.751 e3 mode, the e3-tran : ? inserts the rai bit (bit 11 of the frame) either via a register bit or, optionally, when the e3-frmr declares oof. ? inserts the national use reserved bit (bit 12 of the frame) either as a fixed value through a register bit or from the tdpr block as configured by the tnetop bit in the s/uni-jet data link and ferf control register and the natuse bit in the e3 tran configuration register. ? optionally identifies the tributary justification bits and stuff opportunity bits as either overhead or payload to splt for payload mappings that take advantage of the full bandwidth. further, the e3-tran can provide insertion of bit errors in the framing pattern or in the parity bits, and insertion of single lcv for diagnostic purposes. most of the overhead bits can be overwritten by using the toh[x] and tohins[x] input pins. 10.15 j2 transmitter the j2 transmitter (j2-tran) block integrates circuitry required to insert the overhead bits into an j2 bit stream and produce a b8zs-encoded signal. the j2-tran is directly compatible with the framing format specified in g.704 and ntt technical reference for high-speed digital leased circuit services. the j2-tran generates the frame alignment signal and inserts it into the incoming serial stream. all overhead and status bits in each frame format can be individually controlled by either register bits or by the transmit overhead stream. the j2-tran inserts: ? the crc-5 bits calculated over the preceding multiframe. ? the x-bits through microprocessor programmable register bits. ? the a-bit through a microprocessor programmable register bit. ? the m-bit data link through the tdpr block. ? payload ais or physical layer ais through microprocessor programmable register bits. ? rai over the m-bits, overwriting hdlc frames, by using the xboc block or through automatic activation upon detection of certain remote alarm conditions. the j2-tran allows overwriting of any of the overhead bits by using the toh[x], tohins[x], tohfp[x], and tohclk[x] overhead signals. further, the j2-tran can provide insertion of single bit errors in the framing pattern or in the crc-5 bits, and insertion of single lcv for diagnostic purposes.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 72 document id: pmc-1990267, issue 3 10.16 xboc bit oriented code generator the bit oriented code generator (xboc) block transmits 63 of the possible 64 bit oriented codes (boc) in the c-bit parity feac channel. a boc is a 16-bit sequence consisting of eight ones, a zero, six code bits, and a trailing zero (111111110xxxxxx0) which is repeated as long as the code is not 111111. the code to be transmitted is programmed by writing the xboc code register. the 64 th code (111111) is similar to the hdlc idle sequence and is used to disable the transmission of any bit oriented codes. when transmission is disabled, the feac channel is set to all ones. 10.17 tdpr pmdl transmitter the path maintenance data link transmitter (tdpr) provides a serial data link for the c-bit parity pmdlin ds3, the serial network operator byte or the general purpose datalink in g.832 e3, the national use bit datalink in g.751 e3, or the m-bit datalink in j2. the tdpr is used under microprocessor control to transmit hdlc data frames. it performs all of the data serialization, crc generation, zero-bit stuffing, as well as flag, and abort sequence insertion. upon completion of the message, a crc-ccitt fcs can be appended, followed by flags. if the tdpr transmit data fifo underflows, an abort sequence is automatically transmitted. when enabled, the tdpr continuously transmits flags (01111110) until data is ready to be transmitted. data bytes to be transmitted are written into the tdpr transmit data register. the tdpr automatically begins transmission of data once at least one complete packet is written into its fifo. all complete packets of data will be transmitted if no error condition occurs. after the last data byte of a packet, the crc fcs (if crc insertion has been enabled) and a flag, or just a flag (if crc insertion has not been enabled) is transmitted. the tdpr then returns to the transmission of flag characters until the next packet is available for transmission. the tdpr will also force transmission of the fifo data once the fifo depth has surpassed the programmable upper limit threshold. transmission commences regardless of whether or not a packet has been completely written into the fifo. the user must be careful to avoid overfilling the fifo. underruns can only occur if the packet length is greater than the programmed upper limit threshold because, in such a case, transmission will begin before a complete packet is stored in the fifo. an interrupt can be generated once the fifo depth has fallen below a user-configured lower threshold as an indicator for the user to write more data. interrupts can also be generated if the fifo underflows while transmitting a packet when the fifo is full, or if the fifo is overrun. if there are more than five consecutive ones in the raw transmit data or in the crc data, a zero is stuffed into the serial data output. this prevents the unintentional transmission of flag or abort sequences.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 73 document id: pmc-1990267, issue 3 abort sequences (01111111 sequence where the 0 is transmitted first) can be continuously transmitted at any time by setting a control bit. during packet transmission, an underrun situation can occur if data is not written to the tdpr transmit data register before the previous byte has been depleted. in this case, an abort sequence is transmitted, and the controlling processor is notified by the udr register bit. an abort sequence will also be transmitted if the user overflows the fifo with a packet of length greater than 128 bytes. overflows where other complete packets are still stored in the fifo will not generate an abort. only the packet which caused the overflow is corrupted and an interrupt is generated to the user by the ovr register bit. the other packets remain unaffected. when the tdpr is disabled, a logic one (idle) is inserted in the pmdl. 10.18 splt smds plcp layer transmitter the smds plcp layer transmitter (splt ) block integrates circuitry to support ds1, ds3, e1, and g.751 e3 based plcp frame insertion. the splt automatically inserts the framing (a1, a2) and path overhead identification (pohid) octets and provides registers or automatic generation of the f1, b1, g1, m2, m1, and c1 octets. registers are provided for the path user channel octet (f1) and the path status octet (g1). the bit interleaved parity octet (b1) and the febe subfield are automatically inserted. the dqdb management information octets, m1 and m2 are generated. the type 0 and type 1 patterns described in ta-tsy-000772 are automatically inserted. the type 1 page counter may be reset using a register bit in the splt configuration register. note: this feature is not required for the atm forum compliant ds3 uni. for this application, the m1 and m2 octets must be set to all zeros. the plcp transmit frame c1 cycle/stuff counter octet and the transmit stuffing pattern can be referenced to the ref8ki input pin. alternately, a fixed stuffing pattern may be inserted into the c1 cycle/stuff counter octet. a looped timing operating mode is provided where the transmit plcp timing is derived from the received timing. in this mode, the c1 stuffing is generated based on the received stuffing pattern as determined by the splr block. when ds1 or e1 plcp format is enabled, the pattern 00h is inserted. when ds3 plcp format is enabled, the c1 octet indicates the phase of the 375 s nibble stuffing opportunity cycle. during frame one of the three frame cycle, the pattern ffh is inserted in the c1 octet, indicating a 13 nibble trailer length. during frame two, the pattern 00h is inserted, indicating a 14 nibble trailer length. during frame three, the pattern 66h or 99h is inserted, indicating a 13 or 14 nibble trailer length respectively. when configured for g.751 e3 plcp frame format, the c1 octet is used to indicate the number of octets stuffed in the trailer. the table 5 shows the c1 octet pattern for each of the possible octet stuff lengths:
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 74 document id: pmc-1990267, issue 3 table 5 c1 octet pattern stuff length c1(hex) 17 3b 18 4f 19 75 20 9d 21 a7 the splt block generates a stuff length pattern of 18, 19, or 20 octets determined by the phase alignment of the start of the g.751 e3 frame and the start of the e3 plcp frame. the ref8ki input is provisioned to loop time the plcp transmit frame to an externally applied 8 khz reference. the zn, growth octets are set to 00h. the zn octets may be inserted from an external device via the path overhead stream input, tpoh. 10.19 txcp-50 transmit cell processor the transmit cell processor (txcp-50) block integrates circuitry to support atm cell payload scrambling, header check sequence (hcs) generation, and idle/unassigned cell generation. the txcp-50 scrambles the cell payload field using the self synchronizing scrambler with polynomial x 43 + 1. the header portion of the cells may also be scrambled. note: cell payload scrambling may be disabled in the s/uni-jet, although it is required by itu-t recommendation i.432. the atm forum ds3 uni specification requires that cell payloads are scrambled for the ds3 physical layer interface. however, to ensure backwards compatibility with older equipment, the payload scrambling may be disabled. the hcs is generated using the polynomial, x 8 + x 2 + x + 1. the coset polynomial x 6 + x 4 + x 2 + 1 is added (modulo 2) to the calculated hcs octet as required by the atm forum uni specification, and itu-t recommendation i.432. the resultant octet optionally overwrites the hcs octet in the transmit cell. when the transmit fifo is empty, the txcp-50 inserts idle/unassigned cells. the idle/unassigned cell header is fully programmable using five internal registers. similarly, the 48-octet information field is programmed with an 8-bit repeating pattern using an internal register. 10.20 txff transmit fifo the transmit fifo (txff) provides fifo management and the s/uni-jet transmit cell interface. the transmit fifo contains four cells. the fifo depth may be programmed to four, three, two, or one cells. the fifo provides the cell rate decoupling function between the transmission system physical layer and the atm layer. the general management functions of the txff include: ? emptying cells from the transmit fifo. ? indicating when the transmit fifo is full.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 75 document id: pmc-1990267, issue 3 ? maintaining the transmit fifo read and write pointers. ? detecting a fifo overrun condition. the fifo interface is ?utopia level 2? compliant and accepts a write clock (tfclk), a write enable signal (tenb), the start of a cell (tsoc) indication, and the parity bit (tprty), and the atm device address (tadr[4:0]) when data is written to the transmit fifo (using the rising edges of tfclk). the interface provides the transmit cell available status (tca and dtca[4:1]), which can transition from "available" to "unavailable" when the transmit fifo is near full (when tcalevel0 is logic zero) or when the fifo is full (when tcalevel0 is logic one) and can accept no more writes. to reduce fifo latency, the fifo depth at which tca and dtca[x] indicates "full" can be set to one, two, three, or four cells by the fifodp[1:0] bits of txcp-50 configuration 2 register. if the programmed depth is less than four, more than one cell may be written after tca or dtca[x] is asserted as the txcp-50 still allows four cells to be stored in its fifo. this interface also indicates fifo overruns via a maskable interrupt and register bit, but write accesses while tca or dtca[x] is logic zero are not processed. the txff automatically transmits idle cells until a full cell is available to be transmitted. 10.21 ttb trail trace buffer the trail trace buffer (ttb) extracts and sources the trail trace message carried in the tr byte of the g.832 e3 stream. the message is used by the os to prevent delivery of traffic from the wrong source and is 16 bytes in length. the 16-byte message is framed by the pti multiframe alignment signal (tmfas = 'b10000000 00000000). one bit of the tmfas is placed in the most significant bit of each message byte. in the receive direction, the trail trace message is extracted from the serial overhead stream output by the e3-frmr. the extracted message is stored in the internal ram for review by an external microprocessor. by default, the ttb will write the byte of a 16-byte message with its most significant bit set high to the first location in the ram. the extracted trail trace message is checked for consistency between consecutive multiframes. a message received unchanged three or five times (programmable) is accepted for comparison with the copy previously written into the internal ram by the external microprocessor. alarms are raised to indicate reception of unstable and mismatched messages. in the transmit direction, the ttb sources the trail trace message from the internal ram for insertion into the tr byte by the e3-tran. the ttb also extracts the payload type label carried in the ma byte of the g.832 e3 stream. the label is used to ensure that the adaptation function at the trail termination sink is compatible with the adaptation function at the trail termination source. the payload type label is check for consistency between consecutive multiframes. a payload type label received unchanged for five frames is accepted for comparison with the copy previously written into the ttb by the external microprocessor. alarms are raised to indicate reception of unstable and mismatched payload type label bits. 10.22 jtag test access port the jtag test access port block provides jtag support for boundary scan. the standard jtag extest, sample, bypass, idcode, and stctest instructions are supported.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 76 document id: pmc-1990267, issue 3 the s/uni-jet identification code is 073460cd hexadecimal. 10.23 microprocessor interface the microprocessor interface block provides normal and test mode registers, and the logic required to connect to the microprocessor interface. normal mode registers are required for normal operation. test mode registers are used to enhance the testability of the s/uni-jet. with the exception of the s/uni-jet identification register, all register descriptions can be found in the s/uni-jet datasheet (pmc-1990267). the register set is accessed as described in table 6. table 6 register memory map address register 000h-2ffh reserved 300h s/uni-jet configuration 1 301h s/uni-jet configuration 2 302h s/uni-jet transmit configuration 303h s/uni-jet receive configuration 304h s/uni-jet data link and ferf/rai control 305h s/uni-jet interrupt status 006h s/uni-jet identification, master reset, and global monitor update 306h s/uni-jet reserved 307h s/uni-jet clock activity monitor and interrupt identification 308h splr configuration 309h splr interrupt enable 30ah splr interrupt status 30bh splr status 30ch splt configuration 30dh splt control 30eh splt diagnostics and g1 octet 30fh splt f1 octet 310h pmon change of pmon performance meters 311h pmon interrupt enable/status 312h-313h pmon reserved 314h pmon lcv event count lsb 315h pmon lcv event count msb 316h pmon framing bit error event count lsb 317h pmon framing bit error event count msb 318h pmon excessive zeros count lsb 319h pmon excessive zeros count msb
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 77 document id: pmc-1990267, issue 3 address register 31ah pmon parity error event count lsb 31bh pmon parity error event count msb 31ch pmon path parity error event count lsb 31dh pmon path parity error event count msb 31eh pmon febe/j2-exzs event count lsb 31fh pmon febe/j2-exzs event count msb 320h cppm reserved 321h cppm change of cppm performance meter 322h cppm bip error count lsb 323h cppm bip error count msb 324h cppm plcp framing error event count lsb 325h cppm plcp framing error event count msb 326h cppm plcp febe count lsb 327h cppm plcp febe count msb 328h-32fh cppm reserved 330h ds3 frmr configuration 331h ds3 frmr interrupt enable 332h ds3 frmr interrupt status 333h ds3 frmr status 334h ds3 tran configuration 335h ds3 tran diagnostics 336h-337h ds3 tran reserved 338h e3 frmr framing options 339h e3 frmr maintenance options 33ah e3 frmr framing interrupt enable 33bh e3 frmr framing interrupt indication and status 33ch e3 frmr maintenance event interrupt enable 33dh e3 frmr maintenance event interrupt indication 33eh e3 frmr maintenance event status 33fh e3 frmr reserved 340h e3 tran framing options 341h e3 tran status and diagnostic options 342h e3 tran bip-8 error mask 343h e3 tran maintenance and adaptation options 344h j2 frmr configuration 345h j2 frmr status 346h j2 frmr alarm interrupt enable 347h j2 frmr alarm interrupt status 348h j2 frmr error/x-bit interrupt enable
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 78 document id: pmc-1990267, issue 3 address register 349h j2 frmr error/x-bit interrupt status 34ah-34bh j2 frmr reserved 34ch j2 tran configuration 34dh j2 tran diagnostics 34eh j2 tran ts97 signaling 34fh j2 tran ts98 signaling 350h rdlc configuration 351h rdlc interrupt control 352h rdlc status 353h rdlc data 354h rdlc primary address match 355h rdlc secondary address match 356h rdlc reserved 357h rdlc reserved 358h tdpr configuration 359h tdpr upper transmit threshold 35ah tdpr lower interrupt threshold 35bh tdpr interrupt enable 35ch tdpr interrupt status/udr clear 35dh tdpr transmit data 35eh-35fh tdpr reserved 360h rxcp-50 configuration 1 361h rxcp-50 configuration 2 362h rxcp-50 fifo/utopia control & config 363h rxcp-50 interrupt enables and counter status 364h rxcp-50 status/interrupt status 365h rxcp-50 lcd count threshold (msb) 366h rxcp-50 lcd count threshold (lsb) 367h rxcp-50 idle cell header pattern 368h rxcp-50 idle cell header mask 369h rxcp-50 corrected hcs error count 36ah rxcp-50 uncorrected hcs error count 36bh rxcp-50 received cell count lsb 36ch rxcp-50 received cell count 36dh rxcp-50 received cell count msb 36eh rxcp-50 idle cell count lsb 36fh rxcp-50 idle cell count 370h rxcp-50 idle cell count msb 371h-37fh rxcp-50 reserved
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 79 document id: pmc-1990267, issue 3 address register 380h txcp-50 configuration 1 381h txcp-50 configuration 2 382h txcp-50 transmit cell status 383h txcp-50 interrupt enable/status 384h txcp-50 idle cell header control 385h txcp-50 idle cell payload control 386h txcp-50 transmit cell counter lsb 387h txcp-50 transmit cell counter 388h txcp-50 transmit cell counter msb 389h-38fh txcp-50 reserved 390h ttb control register 391h ttb trail trace identifier status 392h ttb indirect address register 393h ttb indirect data register 394h ttb expected payload type label register 395h ttb payload type label control/status 396h-397h ttb reserved 398h rboc configuration/interrupt enable 399h rboc status 39ah xboc code 39bh s/uni-jet misc. 39ch s/uni-jet frmr lof status. 3a0h prgd control 3a1h prgd interrupt enable/status 3a2h prgd length 3a3h prgd tap 3a4h prgd error insertion 3a5h-3a7h prgd reserved 3a8h prgd pattern insertion register #1 3a9h prgd pattern insertion register #2 3aah prgd pattern insertion register #3 3abh prgd pattern insertion register #4 3ach prgd pattern detector register #1 3adh prgd pattern detector register #2 3aeh prgd pattern detector register #3 3afh prgd pattern detector register #4 3b0h-3ffh s/uni-jet reserved 400h s/uni-jet master test register 401h-40bh reserved for s/uni-jet test
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 80 document id: pmc-1990267, issue 3 address register 40ch s/uni-jet identification register 40dh - 7ffh reserved for s/uni-jet test notes 1. for all register accesses, csb must be low. 2. writing any value to any of the pmon(314h to 31fh), rxcp-50(369h to 370h) or txcp-50(386h to 388h) counter holding registers will latch the current count value to the holding registers. to ensure that the transfer was completed a wait function must be performed via software as indicated by the specific count registers being latched. each of the above mentioned registers have a specified clock cycle completion requirement that is stated in the specific count registers description. for example the lcv pmon count of registers 314h and 315h specifies that it takes three rclk cycles to complete a transfer of the current count value to the count holding registers. other registers may specify a different clock cycle requirement for the three different operational modes of the jet: ds3, e3 and j2.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 81 document id: pmc-1990267, issue 3 11 normal mode register description normal mode registers are used to configure and monitor the operation of the s/uni-jet . normal mode registers (as opposed to test mode registers) are selected when a[10] is low. notes on normal mode register bits: ? writing values into unused register bits has no effect. however, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. ? all configuration bits that can be written into can also be read back. this allows the processor controlling the s/uni-jet to determine the programming state of the block. ? writable normal mode register bits are cleared to logic zero upon reset unless otherwise noted. ? writing into read-only normal mode register bit locations does not affect s/uni-jet operation unless otherwise noted. ? certain register bits are reserved. these bits are associated with megacell functions that are unused in this application. to ensure that the s/uni-jet operates as intended, reserved register bits must only be written with the suggested logic levels. similarly, writing to reserved registers should be avoided. ? the s/uni-jet requires a software initialization sequence in order to guarantee proper device operation and long term reliability. please refer to section 13.1 of this document for the details on how to program this sequence.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 82 document id: pmc-1990267, issue 3 register 300h: s/uni-jet configuration 1 bit type function default bit 7 r/w 8krefo 1 bit 6 r/w ds27_53 1 bit 5 r/w tocta 0 bit 4 r/w frmronly 0 bit 3 r/w loopt 0 bit 2 r/w lloop 0 bit 1 r/w dloop 0 bit 0 r/w ploop 0 ploop the ploop bit controls the ds3, e3, or j2 payload loopback. when a logic zero is written to ploop, ds3, e3, or j2 payload loopback is disabled. when a logic one is written to ploop, the ds3, e3, or j2 overhead bits are regenerated and inserted into the received ds3, e3, or j2 stream and the resulting stream is transmitted. setting the ploop bit disables the effect of the ticlk bit in the s/uni-jet transmit configuration register, thereby forcing flow- through timing. the tfrm[1:0] and rfrm[1:0] bits in the s/uni-jet transmit configuration and receive configuration registers, respectively, must be set to the same value for ploop to work properly. dloop the dloop bit controls the diagnostic loopback. when a logic zero is written to dloop, diagnostic loopback is disabled. when a logic one is written to dloop, the transmit data stream is looped in the receive direction. the tfrm[1:0] and rfrm[1:0] bits in the s/uni- jet transmit configuration and receive configuration registers, respectively, must be set to the same value for dloop to work properly. the dloop should not be set to a logic one when either the ploop, lloop, or loopt bit is a logic one. when in ds3, e3, or j2 modes, the tuni register bit in the s/uni-jet transmit configuration register should be set to the same value as the uni bit in the ds3, e3, or j2 frmr registers. lloop the lloop bit controls the line loopback. when a logic zero is written to lloop, line loopback is disabled. when a logic one is written to lloop, the stream received on rpos/rdati and rneg/rlcv/rohm is looped to the tpos/tdato and tneg/tohm outputs. note: the tpos, tneg, and tclk outputs are referenced to rclk when lloop is logic one.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 83 document id: pmc-1990267, issue 3 loopt the loopt bit selects the transmit timing source. when a logic one is written to loopt, the transmitter is loop-timed to the receiver. when loop timing is enabled, the receive clock (rclk) is used as the transmit timing source. the transmit nibble stuffing is derived from the nibble stuffing in the receive plcp frame (for ds3 or e3 plcp frame transmission). the fixstuff bit must be set to logic zero if the loopt bit is set to logic one. when a logic zero is written to loopt, the transmit clock (ticlk) is used as the transmit timing source. the nibble stuffing is derived from the ref8ki input, or is fixed internally as determined by the fixstuff bit in the splt configuration register (for ds3 or e3 plcp frame transmission only). setting the loopt bit disables the effect of the ticlk and txref bits in the s/uni-jet transmit configuration and s/uni-jet configuration 2 registers respectively, thereby forcing flow-through timing. frmronly the frmronly bit controls whether the s/uni-jet is operating solely as a ds3, e3, or j2 framer/transmitter. if frmronly is set to logic one, the plcp, and atm blocks are disabled and the rdato, ref8ko/rfpo/rmfpo, rsclk, rovrhd, tfpo/tmfpo, tfpi/tmfpi, and tdati i/o pins are enabled. the atm interface inputs are ignored and the outputs are tri-stated. if frmronly is set to logic zero, the plcp and atm blocks are enabled and the lcd, rpoh, rpohclk, rpohfp, tpoh, tiohm, and tpohfp i/o pins are enabled and the atm interface inputs and outputs are enabled. tocta the tocta bit enables octet-alignment or nibble-alignment of the transmit cell stream to the transmission overhead when the arbitrary transmission format is chosen (tfrm[1:0] = 11 binary and splt configuration register bit ext = 1). this bit has no effect when ds3, g.751 e3, g.832 e3, j2, t1, or e1 formats are selected since octet or nibble alignment is specified for these formats. when the arbitrary transmission format is chosen and tocta is set to logic one, the atm cell nibbles or octets are aligned to the arbitrary transmission format overhead boundaries (as set by the tiohm input). nibble alignment is chosen if the form[1:0] bits in the splt configuration are set to 00. byte alignment is chosen if these form[1:0] bits are set to any other value. the number of ticlk periods between transmission format overhead bit positions must be divisible by four (for nibble alignment) or eight (for byte alignment). when tocta is set to logic zero, no octet alignment is performed , and there is no restriction on the number of ticlk periods between transmission format overhead bit positions.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 84 document id: pmc-1990267, issue 3 ds27_53 the ds27_53 bit is used to select between the long data structure (27-byte words in 16-bit mode and 53-byte words in 8-bit mode) and the short data structure (26-byte words in 16-bit mode and 52-byte words in 8-bit mode) on the atm interface. when ds27_53 is set to logic one, the rxcp-50 and txcp-50 blocks are configured to operate with the long data structure; when ds27_53 is set to logic zero, the rxcp-50 and txcp-50 are configured to operate with the short data structure. 8krefo the 8krefo bit is used, in conjunction with the plcpen bit in the splr configuration register to select the function of the ref8ko/rpohfp/rfpo/rmfpo[x] output pin. when plcpen is logic one, the rpohfp function will be selected and 8krefo has no effect. (note: rpohfp is inherently an 8khz reference). if plcpen is logic zero and if 8krefo becomes logic one, then an 8 khz reference will be derived from the rclk[x] signal and output on ref8ko. if 8krefo and plcpen are both logic zero, then the rxmfpo register bit in the s/uni-jet configuration 2 register will select either the rfpo or rmfpo function.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 85 document id: pmc-1990267, issue 3 register 301h: s/uni-jet configuration 2 bit type function default bit 7 r/w statsel[2] 0 bit 6 r/w statsel[1] 0 bit 5 r/w statsel[0] 0 bit 4 r/w txmfpi 0 bit 3 r/w txgapen 0 bit 2 r/w rxgapen 0 bit 1 r/w txmfpo 0 bit 0 r/w rxmfpo 0 rxmfpo the rxmfpo bit controls which of the outputs rmfpo or rfpo is valid. if rxmfpo is a logic one, then rmfpo will be available. if rxmfpo is a logic zero, then rfpo will be available. this bit is effective only if the frmronly bit in the s/uni-jet configuration 1 register is a logic one. txmfpo the txmfpo bit controls which of the outputs tmfpo[4:1] or tfpo[4:1] is valid. if txmfpo is a logic one, then tmfpo[4:1] will be available. if txmfpo is a logic zero, then tfpo[4:1] will be available. this bit is effective only if the frmronly bit in the s/uni-jet configuration 1 register is a logic one. the txgapen bit takes precedence over the txmfpo bit. rxgapen the rxgapen bit configures the s/uni-jet to enable the rgapclk[x] outputs. when rxgapen is a logic one, then the rgapclk[x] output is enabled. when rxgapen is a logic zero, then the rsclk[x] output is enabled. the frmronly register bit must be a logic one for rxgapen to have effect. txgapen the txgapen bit configures the s/uni-jet to enable the tgapclk[x] outputs. when txgapen is a logic one, the tgapclk[x] output is enabled. when txgapen is a logic zero, then either the tfpo[x] or tmfpo[x] output is enabled, depending on the setting of the txmfpo register bit. the frmronly register bit must be a logic one for txgapen to have effect.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 86 document id: pmc-1990267, issue 3 txmfpi the txmfpi bit controls which of the inputs tmfpi or tfpi is valid. if txmfpi is a logic one, then tmfpi will be expected. if txmfpi is a logic zero, then tfpi will be expected. this bit is effective only if the frmronly bit in the s/uni-jet configuration 1 register is a logic one. statsel[2:0] the statsel[2:0] bits are used to select the function of the frmstat output. the selection is shown in table 7: table 7 statsel[2:0] options statsel[2:0] frmstat output pin indication function 000 e3/ds3 lof or j2 extended lof (integration periods are selected by the lofint[1:0] register bits in the s/uni-jet receive configuration register) 001 plcp lof 010 e3/ds3 oof or j2 lof 011 plcp oof 100 ais 101 los 110 ds3 idle 111 reserved
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 87 document id: pmc-1990267, issue 3 register 302h: s/uni-jet transmit configuration bit type function default bit 7 r/w tfrm[1] 0 bit 6 r/w tfrm[0] 0 bit 5 r/w txref 0 bit 4 r/w ticlk 0 bit 3 r/w tuni 0 bit 2 r/w tclkinv 0 bit 1 r/w tposinv 0 bit 0 r/w tneginv 0 tneginv the tneginv bit provides polarity control for outputs tneg/tohm. when a logic zero is written to tneginv, the tneg/tohm output is not inverted. when a logic one is written to tneginv, the tneg/tohm output is inverted. the tneginv bit setting does not affect the loopback data in diagnostic loopback. tposinv the tposinv bit provides polarity control for outputs tpos/tdato. when a logic zero is written to tposinv, the tpos/tdato output is not inverted. when a logic one is written to tposinv, the tpos/tdato output is inverted. the tposinv bit setting does not affect the loopback data in diagnostic loopback. tclkinv the tclkinv bit provides polarity control for output tclk. when a logic zero is written to tclkinv, tclk is not inverted and outputs tpos/tdato and tneg/tohm are updated on the falling edge of tclk. when a logic one is written to tclkinv, tclk is inverted and outputs tpos/tdato and tneg/tohm are updated on the rising edge of tclk. tuni the tuni bit enables the s/uni-jet to transmit unipolar or bipolar ds3, e3, or j2 data streams. when a logic one is written to tuni, the s/uni-jet transmits unipolar ds3, e3, or j2 data on tdato. when tuni is logic one, the tohm output indicates the start of the ds3 m-frame (the x1 bit), the start of the e3 frame (bit 1 of the frame), or the first framing bit of the j2 multiframe. when a logic zero is written to tuni, the s/uni-jet transmits b3zs- encoded ds3 data, hdb3-encoded e3 data, or b8zs-encoded j2 data on tpos and tneg. the tuni bit has no effect if tfrm[1:0] is set to 11 binary as the output data is automatically configured for unipolar format.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 88 document id: pmc-1990267, issue 3 ticlk the ticlk bit selects the transmit clock used to update the tpos/tdato and tneg/tohm outputs. when a logic zero is written to ticlk, the buffered version of the input transmit clock, tclk, is used to update tpos/tdato and tneg/tohm on the edge selected by the tclkinv bit. when a logic one is written to ticlk, tpos/tdato and tneg/tohm are updated on the rising edge of ticlk, eliminating the flow-through tclk signal. the ticlk bit has no effect if the loopt, lloop, or ploop bit is a logic one. txref the txref register bit determines if ticlk[1] and tiohm/tfpi/tmfpi[1] should be used as the reference transmit clock and overhead/frame pulse, respectively, instead of ticlk and tiohm/tfpi/tmfpi. if txref is set to a logic one, then ticlk[1] and tiohm/tfpi/tmfpi[1] will be used as the reference transmit clock and overhead/frame pulse, respectively. if txref is set to a logic zero, then ticlk and tiohm/tfpi/tmfpi will be used as the reference transmit clock and overhead/frame pulse, respectively, for quadrant x. if loop-timing is enabled (loopt = 1), the txref bit has no effect on the corresponding quadrant. note: when txref is set to logic one, the unused ticlk and tiohm/tfpi/tmfpi should be tied to power or ground, not left floating. tfrm[1:0] the tfrm[1:0] bits determine the frame structure of the transmitted signal. refer to table 8: table 8 tfrm[1:0] transmit frame structure configurations tfrm[1:0] transmit frame structure 00 ds3 (c-bit parity or m23 depending on the setting of the cbit bit in the ds3 tran configuration register) 01 e3 (g.751 or g.832 depending on the setting of the format[1:0] bits in the e3 tran framing options register) 10 j2 (g.704 and ntt compliant framing format) 11 ds1/e1/arbitrary framing format - if the ext bit in the splt configuration register is a logic zero, then ds1 or e1 direct-mapped or plcp framing is selected (via the plcpen and form[1:0] bits in the splt configuration register) and tiohm should be tied low. if ext is a logic one, then the arbitrary framing format is selected and overhead positions are indicated by the tiohm input pin.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 89 document id: pmc-1990267, issue 3 register 303h: s/uni-jet receive configuration bit type function default bit 7 r/w rfrm[1] 0 bit 6 r/w rfrm[0] 0 bit 5 r/w lofint[1] 0 bit 4 r/w lofint[0] 0 bit 3 r/w rsclkr 0 bit 2 r/w rclkinv 0 bit 1 r/w rposinv 0 bit 0 r/w rneginv 0 rneginv the rneginv bit provides polarity control for input rneg/rlcv/rohm. when a logic zero is written to rneginv, the input rneg/rlcv/rohm is not inverted. when a logic one is written to rneginv, the input rneg/rlcv/rohm is inverted. the rneginv bit setting does not affect the loopback data in diagnostic loopback. rposinv the rposinv bit provides polarity control for input rpos/rdati. when a logic zero is written to rposinv , the input rpos/rdati is not inverted. when a logic one is written to rposinv , the input rpos/rdati is inverted. the rposinv bit setting does not affect the loopback data in diagnostic loopback. rclkinv the rclkinv bit provides polarity control for input rclk. when a logic zero is written to rclkinv, rclk is not inverted and inputs rpos/rdati and rneg/rlcv/rohm are sampled on the rising edge of rclk. when a logic one is written to rclkinv, rclk is inverted and inputs rpos/rdati and rneg/rlcv/rohm are sampled on the falling edge of rclk. rsclkr the rsclkr bit is in effect only when the frmronly bit in the s/uni-jet configuration 1 register is set to logic one. when rsclkr is a logic one, the rdato, rfpo/rmfpo, and rovrhd outputs are updated on the rising edge of rsclk. when rsclkr is a logic zero, the rdato, rfpo/rmfpo, and rovrhd outputs are updated on the falling edge of rsclk. if the rxgapen bit is a logic one, then rsclkr affects rgapclk in the same manner as it affects rsclk.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 90 document id: pmc-1990267, issue 3 lofint[1:0] the lofint[1:0] bits determine the integration period used for asserting and de-asserting e3 and ds3 lof or j2 extended lof on the frmlof register bit of the s/uni-jet frmr lof status register (x9ch) and on the frmstat[4:1] output pins (if this function is enabled by the statsel[2:0] register bits of the s/uni-jet configuration 2 register). the integration times are selected as shown in table 9: table 9 lof[1:0] integration period configuration lofint[1:0] integration period 00 3 ms 01 2 ms 10 1 ms 11 reserved rfrm[1:0] the rfrm[1:0] bits determine the expected frame structure of the received signal. refer to table 10: table 10 rfrm[1:0] receive frame structure configurations rfrm[1:0] expected receive frame structure 00 ds3 (c-bit parity or m23 depending on the setting of the cbe bit in the ds3 frmr configuration register) 01 e3 (g.751 or g.832 depending on the setting of the format[1:0] bits in the e3 frmr framing options register) 10 j2 (g.704 and ntt compliant framing format) 11 ds1/e1/arbitrary framing format (when ext in the splr configuration register is a logic zero, then ds1 or e1 direct-mapped or plcp framing is selected (via the plcpen and form[1:0] bits in the splr configuration register) and the frame alignment is indicated by the rohm[x] input pin. when ext is a logic one, then the arbitrary framing format is selected and overhead bit positions are indicated by the rohm[x] input pin.)
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 91 document id: pmc-1990267, issue 3 register 304h: s/uni-jet data link and ferf/rai control bit type function default bit 7 r/w lcden 1 bit 6 r/w aisen 1 bit 5 r/w rblen 1 bit 4 r/w oofen 1 bit 3 r/w losen 1 bit 2 r/w tnetop 0 bit 1 r/w rnetop 0 bit 0 r/w dlinv 0 dlinv the dlinv bit provides polarity control for the ds3 c-bit parity pmdl, which is located in the three c-bits of m-subframe 5. when a logic one is written to dlinv, the pmdl is inverted before being processed. the rationale behind this bit is to safe-guard the s/uni-jet in case the inversion is required in the future. currently, the ansi standard t1.107 specifies that the c-bits, which carry the pmdl, be set to all-zeros while the ais maintenance signal is transmitted. the data link is obviously inactive during ais transmission, and ideally the hdlc idle sequence (all ones) should be transmitted. by inverting the data link, the all-zeros c-bit pattern becomes an idle sequence and the data link is terminated gracefully. rnetop the rnetop bit enables the network operator byte (nr) extracted from the g.832 e3 stream to be terminated by the internal hdlc receiver, rdlc. when rnetop is logic one, the nr byte is extracted from the g.832 stream and terminated by rdlc. when rnetop is logic zero, the gc byte is extracted from the g.832 stream and terminated by rdlc. both the nr byte and the gc byte are extracted and output on the roh pin for external processing. tnetop the tnetop bit enables the network operator byte (nr) inserted in the g.832 e3 stream to be sourced by the internal hdlc transmitter, tdpr. when tnetop is logic one, the nr byte is inserted into the g.832 stream through the tdpr block; the gc byte of the g.832 e3 stream is sourced by through the toh and tohins pins. if toh and tohins are not active, then an all-ones signal will be inserted into the gc byte. when tnetop is logic zero, the gc byte is inserted into the g.832 stream through the tdpr block; the nr byte of the g.832 e3 stream is sourced by the toh and tohins pins. if toh and tohins are not active, then an all-ones signal will be inserted into the nr byte.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 92 document id: pmc-1990267, issue 3 for g.751 e3 streams, the national use bit is sourced by the tdpr block if tnetop and the natuse bit (from the e3 tran configuration register 341h) are both logic zero. if either tnetop or natuse is logic one, the national use bit will be sourced from the natuse register bit in register 341h. if the s/uni-jet is configured for ds3 or j2 operation, tnetop has no effect. the ds3 c- bit parity and j2 datalink is inserted into the ds3 or j2 stream through the internal hdlc transmitter tdpr. the toh and tohins input pins can be used to overwrite the values of these overhead bits in the transmit stream. losen the losen bit enables the receive los indication to automatically generate a ferf indication in the transmit stream. this bit operates regardless of framer selected (ds3, e3, or j2). when losen is logic one, assertion of the los indication by the framer causes a ferf (rai in g.751 or j2 mode) to be transmitted by tran for the duration of the los assertion. when losen is logic zero, assertion of the los indication does not cause transmission of a ferf/rai. note: for the rai to be automatically transmitted when in j2 format, the feac[5:0] bits in the xboc code register must all be set to logic one. if the xboc feac code is to be transmitted in j2 mode, losen, oofen, aisen, and lcden should all be set to logic zero. oofen the oofen bit enables the receive oof indication to automatically generate a ferf indication (rai in g.751 or j2 mode) in the transmit stream. this bit operates when the e3 or j2 framer is selected or when the ds3 framer is selected and the rblen bit is logic zero. when oofen is logic one, assertion of the oof indication by the framer causes a ferf/rai to be transmitted by tran for the duration of the oof assertion. when oofen is logic zero, assertion of the oof indication does not cause transmission of a ferf/rai. note: for the rai to be automatically transmitted when in j2 format, the feac[5:0] bits in the xboc code register must all be set to logic one. if the xboc feac code is to be transmitted in j2 mode, losen, oofen, aisen, and lcden should all be set to logic zero.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 93 document id: pmc-1990267, issue 3 rblen the rblen bit enables: the receive red alarm (persistent oof) indication to automatically generate a ferf indication in the ds3 transmit stream, or a bip8 error detection in the e3 g.832 framer to generate a febe indication in the e3 g.832 transmit stream, or an lof to generate a rlof indication (a-bit) in the j2 transmit stream. when the e3 g.751 framer is selected, this bit has no effect. when rblen is logic one, tfrm[1:0] is 00 binary, and rfrm[1:0] is 00 binary, assertion of the red indication by the framer causes a ferf to be transmitted by ds3_tran for the duration of the red assertion. also, for ds3 frame format, the oofen bit is internally forced to logic zero when rblen is logic one. when rblen is logic zero, assertion of the red indication does not cause transmission of a ferf. when rblen is logic one, tfrm[1:0] is 01 binary, and rfrm[1:0] is 01 binary, any bip8 error indication by the e3 g.832 framer causes a febe to be generated by the e3 g.832 tran. when rblen is logic zero, bip8 errors detected by the e3 framer do not cause febes to be generated by the e3_tran. when rblen is logic one, tfrm[1:0] is 10 binary, and rfrm[1:0] is 10 binary, any lof error indication by the j2 framer causes the rlof bit (also known as the a bit) to be set in the j2 transmit stream. when rblen is logic zero, lof errors detected by the j2 framer do not cause the rlof bit to be set in the transmit stream. aisen the aisen bit enables the rai signal to automatically generate a ferf indication (rai in g.751 or j2 mode) in the transmit stream. this bit operates regardless of framer selected (ds3, e3, or j2). when aisen is logic one, assertion of the ais indication (physical ais for j2) by the framer causes a ferf/rai to be transmitted by tran for the duration of the ais assertion. when aisen is logic zero, assertion of the ais indication does not cause transmission of a ferf/rai. note: for the rai to be automatically transmitted when in j2 format, the feac[5:0] bits in the xboc code register must all be set to logic one. if the xboc feac code is to be transmitted in j2 mode, losen, oofen, aisen, and lcden should all be set to logic zero.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 94 document id: pmc-1990267, issue 3 lcden the lcden bit enables the receive-out-of-cell-delineation indication to automatically generate a ferf indication (rai in g.751 or j2 mode) in the transmit stream. this bit operates regardless of framer selected (ds3, e3, or j2) but only in atm mode. when lcden is logic one, assertion of the lcd indication by the receive fifo causes a ferf/rai to be transmitted by the transmitter for the duration of the lcd assertion. when lcden is logic zero, assertion of the lcd indication does not cause transmission of a ferf/rai. note: for the rai to be automatically transmitted when in j2 format, the feac[5:0] bits in the xboc code register must all be set to logic one. if the xboc feac code is to be transmitted in j2 mode, losen, oofen, aisen, and lcden should all be set to logic zero.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 95 document id: pmc-1990267, issue 3 register 305h: s/uni-jet interrupt status bit type function default bit 7 r splri/ttbi x bit 6 r txcp50i x bit 5 r rxcp50i x bit 4 r rboci/prgdi x bit 3 r frmri/lofi x bit 2 r pmoni x bit 1 r tdpri x bit 0 r rdlci x splri/ttbi, txcp50i, rxcp50i, rboci/prgdi, frmri/lofi, pmoni, tdpri, rdlci these bits are interrupt status indicators that identify the block that is the source of a pending interrupt. the splri/ttbi bit will be logic one if either the splr or the ttb block has produced the interrupt. the rboci/prgdi bit will be logic one if either the rboc or prgd block has produced the interrupt. the frmri/lofi will be logic one if either the frmr (j2, e3, or t3 - whichever one is enabled) or the e3, t3, or j2 extended lof signal (frmlofi from register x9ch) is the source of the interrupt. this register is typically used by interrupt service routines to determine the source of a s/uni-jet interrupt.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 96 document id: pmc-1990267, issue 3 register 006h: s/uni-jet identification, master reset, and global monitor update bit type function default bit 7 r/w reset 0 bit 6 r type[3] 1 bit 5 r type[2] 0 bit 4 r type[1] 0 bit 3 r type[0] 0 bit 2 r unused x bit 1 r id[1] 1 bit 0 r id[0] 0 this register is used for global performance monitor updates, global software resets, and for device identification. writing any value except 80h into this register initiates latching of all performance monitor counts in the pmon, rxcp-50, and txcp-50 blocks in all four quadrants of the s/uni-jet. the tip register bit is used to signal when the latching is complete. the cppm counter registers are not latched by writing to register 006h. counters in the cppm can only be updated by writing to cppm register addresses (322h ? 32fh). id[1:0] the id[1:0] bits allows software to identify the version level of the s/uni-jet. type[3:0] the type[3:0] bits allow software to identify this device as the s/uni-jet member of the s/uni family of products. reset the reset bit allows software to asynchronously reset the s/uni-jet. the software reset is equivalent to setting the rstb input pin low, except that the s/uni-jet master test register is not affected. when a logic one is written to reset, the s/uni-jet is reset. when a logic zero is written to reset, the reset is removed. the reset bit must be explicitly set and cleared by writing the corresponding logic value to this register.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 97 document id: pmc-1990267, issue 3 register 307h: s/uni-jet clock activity monitor and interrupt identification bit type function default bit 7 r int x bit 6 r unused x bit 5 r unused x bit 4 r unused x bit 3 r rclka x bit 2 r ticlka x bit 1 r tfclka x bit 0 r rfclka x rfclka the rfclka bit monitors for low-to-high transitions on the rfclk input. rfclka is set low when this register is read and is set high on a rising edge of rfclk. tfclka the tfclka bit monitors for low-to-high transitions on the tfclk input. tfclka is set low when this register is read and is set high on a rising edge of tfclk. ticlka the ticlka bit monitors for low-to-high transitions on the ticlk input. ticlka is set low when this register is read and is set high on a rising edge of ticlk. rclka the rclka bit monitors for low-to-high transitions on the rclk input. rclka is set low when this register is read and is set high on a rising edge of rclk. int when the int bit is set to logic one, the s/un-jet has generated the interrupt. the particular block(s) the device that generated the interrupt can be identified by reading the s/uni-jet interrupt status register. when the int bit is set to logic zero, then the device has not generated an interrupt. note: the int bit is valid only in register address 307h.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 98 document id: pmc-1990267, issue 3 register 308h: splr configuration bit type function default bit 7 r/w form[1] 0 bit 6 r/w form[0] 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reframe 0 bit 2 r/w plcpen 0 bit 1 unused x bit 0 r/w ext 0 ext the ext bit disables the internal transmission system sublayer timeslot counter from identifying ds1, ds3, e1, j2, e3 g.751, or e3 g.832 overhead bits. the ext bit allows transmission formats that are unsupported by the internal timeslot counter to be supported using the rohm[x] input. when a logic zero is written to ext, input transmission system overhead (for ds1, ds3, e1, j2, e3 g.751, and e3 g.832 formats) is indicated using the internal timeslot counter. this counter is synchronized to the transmission system frame alignment using the rohm[x] (for ds1 or e1 atm direct-mapped formats), or by the integral framer block (for the ds3, j2, e3 g.751, or e3 g.832 formats). when a logic one is written to ext, indications on rohm identify each transmission system overhead bit. plcpen the plcpen bit enables plcp framing. when a logic one is written to plcpen, plcp framing is enabled. the plcp format is specified by the form[1:0] bits in this register. when a logic zero is written to plcpen, plcp related functions in the splr block are disabled. plcpen must be programmed to logic zero for e3 g.832, j2, and arbitrary framing formats. reframe the reframe bit is used to trigger reframing. when a logic one is written to reframe, the s/uni-jet is forced out of plcp frame and a new search for frame alignment is initiated. note: only a logic zero to logic one transition of the reframe bit triggers reframing; multiple write operations are required to ensure such a transition. reserved all reserved bits must be set to logic zero for proper operation.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 99 document id: pmc-1990267, issue 3 form[1:0] the form[1:0] bits select the plcp frame format as shown below. these bits must be set to ?11? if e1 direct mapped mode is being used (plcpen=0 and ext=1). refer to table 11. table 11 splr form[1:0] configurations form[1] form[0] plcp framing format 00 ds3 0 1 e3 g.751 10 ds1 11 e1
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 100 document id: pmc-1990267, issue 3 register 309h: splr interrupt enable bit type function default bit 7 unused x bit 6 r/w febee 0 bit 5 r/w colsse 0 bit 4 r/w bipee 0 bit 3 r/w fee 0 bit 2 r/w yele 0 bit 1 r/w lofe 0 bit 0 r/w oofe 0 oofe the oofe bit enables interrupt generation when a plcp oof defect is declared or removed. the interrupt is enabled when a logic one is written. lofe the lofe bit enables interrupt generation when a plcp lof defect is declared or removed. the interrupt is enabled when a logic one is written. yele the yele bit enables interrupt generation when a plcp yellow alarm defect is declared or removed. the interrupt is enabled when a logic one is written. fee the fee bit enables interrupt generation when the s/uni-jet detects a plcp framing octet error. the interrupt is enabled when a logic one is written. bipee the bipee bit enables interrupt generation when the s/uni-jet detects a plcp bit interleaved parity error. the interrupt is enabled when a logic one is written. colsse the colsse bit enables interrupt generation when the s/uni-jet detects a change of plcp link status. the interrupt is enabled when a logic one is written.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 101 document id: pmc-1990267, issue 3 febee the febee bit enables interrupt generation when the s/uni-jet detects a plcp febe. the interrupt is enabled when a logic one is written.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 102 document id: pmc-1990267, issue 3 register 30ah: splr interrupt status bit type function default bit 7 unused x bit 6 r febei x bit 5 r colssi x bit 4 r bipei x bit 3 r fei x bit 2 r yeli x bit 1 r lofi x bit 0 r oofi x oofi the oofi bit is set to logic one when a plcp oof defect is detected or removed. the oof defect state is contained in the splr status register. the oofi bit position is set to logic zero when this register is read. lofi the lofi bit is set to logic one when a plcp lof defect is detected or removed. the lof defect state is contained in the splr status register. the lofi bit position is set to logic zero when this register is read. yeli the yeli bit is set to logic one when a plcp yellow alarm defect is detected or removed. the yellow alarm defect state is contained in the splr status register. the yeli bit position is set to logic zero when this register is read. fei the fei bit is set to logic one when a plcp framing octet error is detected. a framing octet error is generated when one or more errors are detected in the framing alignment octets (a1, and a2), or the path overhead identification octets. the fei bit position is set to logic zero when this register is read. bipei the bipei bit is set to logic one when a plcp bit interleaved parity (bip) error is detected. bip errors are detected using the b1 byte in the plcp path overhead. the bipei bit position is set to logic zero when this register is read.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 103 document id: pmc-1990267, issue 3 colssi the colssi bit is set to logic one when a plcp change of link status signal code is detected. the link status signal code is contained in the path status octet (g1). link status signal codes are required in systems implementing the ieee-802.6 dqdb protocol. a change of link status event occurs when two consecutive and identical link status codes are received that differ from the current code. the colssi bit position is set to logic zero when this register is read. febei the febei bit is set to logic one when a plcp febe (febe) is detected. febe errors are indicated in the plcp path status octet (g1). the febei bit position is set to logic zero when this register is read.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 104 document id: pmc-1990267, issue 3 register 30bh: splr status bit type function default bit 7 unused x bit 6 r lss[2] x bit 5 r lss[1] x bit 4 r lss[0] x bit 3 unused x bit 2 r yelv x bit 1 r lofv x bit 0 r oofv x oofv the oofv bit indicates the current plcp oof defect state. when an error is detected in both the a1 and a2 octets or when an error is detected in two consecutive path overhead identifier octets, oofv is set to logic one. when the s/uni-jet has found two valid, consecutive sets of a1 and a2 octets with two valid and sequential path overhead identifier octets, the oofv bit is set to logic zero. lofv the lofv bit indicates the current plcp lof defect state. the lof defect state is an integrated version of the oof defect state. the declaration/removal times for the lof defect state depends on the selected plcp format. these are summarized in table 12: table 12 plcp lof declaration/removal times plcp format declaration (ms) removal (ms) ds3 1 12 e3 g.751 1.12 10 ds1 25 250 e1 20 200 if the oof defect state is transient, the lof counter is decremented at a rate 1/12 (ds3 plcp) or 1/10 (ds1 or e1 plcp) or 1/9 (g.751 e3 plcp) of the incrementing rate. yelv the yelv bit indicates the current plcp yellow alarm defect state. yelv is set to a logic one when ten or more consecutive frames are received with the yellow bit (contained in the path status octet) set to a logic one. yelv is set to a logic zero when ten or more consecutive frames are received with the yellow bit (contained in the path status octet) set to a logic zero.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 105 document id: pmc-1990267, issue 3 lss[2:0] the lss[2:0] bits contain the current link status signal code. link status signal codes are required in systems implementing the ieee-802.6 dqdb protocol. lss[2:0] is updated when two consecutive and identical link status signal codes are received.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 106 document id: pmc-1990267, issue 3 register 30ch: splt configuration bit type function default bit 7 r/w form[1] 0 bit 6 r/w form[0] 0 bit 5 r/w m1type 0 bit 4 r/w m2type 0 bit 3 r/w fixstuff 0 bit 2 r/w plcpen 0 bit 1 unused x bit 0 r/w ext 0 ext the ext bit disables the internal transmission system sublayer timeslot counter from identifying ds1, ds3, e1, j2, e3 g.751, or e3 g.832 overhead bits. the ext bit allows transmission formats that are unsupported by the internal timeslot counter and must be supported using the tiohm input. when a logic zero is written to ext, input transmission system overhead (for ds1, ds3, e1, j2, e3 g.751, and e3 g.832 formats) is indicated using the internal timeslot counter. this counter ?flywheels? to create the appropriate transmission system alignment. this alignment is indicated on the tohm output. when a logic one is written to ext, indications on tiohm identify each transmission system overhead bit. these indications flow through the s/uni-jet and appear on the tohm output where they mark the transmission system overhead placeholder positions in the tdato stream. ext should only be set to logic one if the tfrm[1:0] bits in the s/uni-jet transmit configuration register are both set to logic one and the arbitrary framing format is desired. plcpen the plcpen bit enables plcp frame insertion. when a logic one is written to plcpen, ds3, e3 g.751, ds1, or e1 plcp framing is inserted. the plcp format is specified by the form[1:0] bits in this register. when a logic zero is written to plcpen, plcp related functions in the splt block are disabled. the plcpen bit must be set to logic zero for g.832 e3, j2, and arbitrary framing formats.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 107 document id: pmc-1990267, issue 3 fixstuff the fixstuff bit controls the transmit plcp frame octet/nibble stuffing used for ds3 and g.751 e3 plcp frame formats. when a logic zero is written to fixstuff, stuffing is determined by the ref8ki input. when a logic one is written to fixstuff and the ds3 plcp frame format is enabled, a nibble is stuffed into the 13 nibble trailer twice every three stuff opportunities (i.e. 13, 14, 14 nibbles). this stuff ratio provides for a nominal plcp frame rate of 125.0002366 s (an error of 1.9 ppm). when the g.751 e3 plcp frame format is enabled, 18, 19 or 20 octets are stuffed into the trailer depending on the alignment of the g.751 e3 frame, and the g.751 e3 plcp frame. this yields a nominal plcp frame rate of 125 s. m2type the m2type bit selects the type of code transmitted in the m2 octet. these codes are required in systems implementing the ieee-802.6 dqdb protocol. when a logic zero is written to m2type, the fixed pattern type 0 code is transmitted in the m2 octet. when a logic one is written to m2type, the 1023 cyclic code pattern (starting with b6 hexadecimal and ending with 8d hexadecimal) is transmitted in the m2 octet. please refer to ta-tsy-000772, issue 3 and supplement 1, for details on the codes. m1type the m1type bit selects the type of code transmitted in the m1 octet. these codes are required in systems implementing the ieee-802.6 dqdb protocol. when a logic zero is written to m1type, the fixed pattern type 0 code is transmitted in the m1 octet. when a logic one is written to m1type, the 1023 cyclic code pattern (starting with b6 hexadecimal and ending with 8d hexadecimal) is transmitted in the m1 octet. please refer to ta-tsy-000772, issue 3 and supplement 1, for details on the codes. form[1:0] when ext = 0 and plcpen = 0, the form[1:0] bits and the tfrm[1:0] bits in the s/uni- jet transmit configuration register select the atm direct-mapped transmission frame format as shown below. when ext = 0 and plcpen = 1, the form[1:0] bits along with the tfrm[1:0] bits select the transmission and plcp frame format as shown below. when ext = 1 and tocta = 1, then the form[1:0] bits control the cell alignment with respect to the transmission overhead given on tiohm as shown in table 13. the form bits have no effect if ext = 1 and tocta = 0. table 13 splt form[1:0] configurations form[1] form[0] plcp or atm direct-mapped framing format / cell alignment 00ds3 / nibble 0 1 e3 or j2 / byte
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 108 document id: pmc-1990267, issue 3 form[1] form[0] plcp or atm direct-mapped framing format / cell alignment 1 0 ds1 / byte 1 1 e1 / byte
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 109 document id: pmc-1990267, issue 3 register 30dh: splt control bit type function default bit 7 unused x bit 6 r/w srczn 0 bit 5 r/w srcf1 0 bit 4 r/w srcb1 0 bit 3 r/w srcg1 0 bit 2 r/w srcm1 0 bit 1 r/w srcm2 0 bit 0 r/w srcc1 0 srcc1 the srcc1 bit value ored with input tpohins selects the source for the c1 octet on a bit by bit basis. if the or results in a logic zero, the c1 bit position is derived internally as specified by the fixstuff bit in the splt configuration register. if the or results in a logic one, the c1 bit position is inserted with the value sampled on tpoh. srcm2 the srcm2 bit value ored with input tpohins selects the source for the m2 octet on a bit by bit basis. if the or results in a logic zero, the m2 bit position is derived internally as specified by the m2type bit in the splt configuration register. if the or results in a logic one, the m2 bit position is inserted with the value sampled on tpoh. the m2 octet is set to logic zero (as required by the atm forum user network interface specification) by writing this bit position with a logic one, and connecting the tpoh input to vss. srcm1 the srcm1 bit value ored with input tpohins selects the source for the m1 octet on a bit by bit basis. if the or results in a logic zero, the m1 bit position is derived internally as specified by the m1type bit in the splt configuration register. if the or results in a logic one, the m1 bit position is inserted with the value sampled on tpoh. the m1 octet is set to logic zero (as required by the atm forum user network interface specification) by writing this bit position with a logic one, and connecting the tpoh input to vss. srcg1 the srcg1 bit value ored with input tpohins selects the source for the g1 octet on a bit by bit basis. if the or results in a logic zero, the g1 bit position is derived internally as required. if the or results in a logic one, the g1 bit position is inserted with the value sampled on tpoh.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 110 document id: pmc-1990267, issue 3 srcb1 the srcb1 bit value ored with input tpohins selects the source for the b1 octet on a bit by bit basis. if the or results in a logic zero, the internally calculated bit interleaved parity value is inserted in the b1 bit position. if the or results in a logic one, the b1 bit position is inserted with the value sampled on tpoh. srcf1 the srcf1 bit value ored with input tpohins selects the source for the f1 octet on a bit by bit basis. if the or results in a logic zero, the f1 bit position is determined by the splt f1 octet register. if the or results in a logic one, the f1 bit position is inserted with the value sampled on tpoh. srczn the srczn bit value ored with input tpohins selects the source for the zn octets (where n=1 to 4 for the ds1 or e1 plcp frame formats, n=1 to 6 for the ds3 plcp frame format, and n=1 to 3 for the g.751 e3 plcp frame format) on a bit by bit basis. if the or results in a logic zero, the zn bit position is forced to a logic zero. if the or results in a logic one, the zn bit position is inserted with the value sampled on tpoh.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 111 document id: pmc-1990267, issue 3 register 30eh: splt diagnostics and g1 octet bit type function default bit 7 r/w dpfrm 0 bit 6 r/w dafrm 0 bit 5 r/w db1 0 bit 4 r/w dfebe 0 bit 3 r/w yel 0 bit 2 r/w lss[2] 0 bit 1 r/w lss[1] 0 bit 0 r/w lss[0] 0 lss[2:0] the lss[2:0] bits control the value inserted in the link status signal code bit positions of the path status octet (g1). these bits should be written with logic zero when implementing an atm forum uni-compliant ds3 interface. yel the yel bit controls the yellow signal bit position in the path status octet (g1). when a logic one is written to yel, the plcp yellow alarm signal is transmitted. dfebe the dfebe bit controls the insertion of febes in the plcp frame. when dfebe is written with a logic one, a single febe is inserted each plcp frame. when dfebe is written with a logic zero, febes are indicated based on receive plcp bit interleaved parity errors. db1 the db1 bit controls the insertion of bit interleaved parity (bip) errors in the plcp frame. when db1 is written with a logic one, a single bip error is inserted in each plcp frame. when db1 is written with a logic zero, the bit interleaved parity is calculated and inserted normally. dafrm the dafrm bit controls the insertion of frame alignment pattern errors. when dafrm is written with a logic one, a single bit error is inserted in each a1 octet, and in each a2 octet. when dafrm is written with a logic zero, the frame alignment pattern octets are inserted normally.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 112 document id: pmc-1990267, issue 3 dpfrm the dpfrm bit controls the insertion of parity errors in the path overhead identification (pohid) octets. when dpfrm is written with a logic one, a parity error is inserted in each pohid octet. when dpfrm is written with a logic zero, the pohid octets are inserted normally.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 113 document id: pmc-1990267, issue 3 register 30fh: splt f1 octet bit type function default bit 7 r/w f1[7] 0 bit 6 r/w f1[6] 0 bit 5 r/w f1[5] 0 bit 4 r/w f1[4] 0 bit 3 r/w f1[3] 0 bit 2 r/w f1[2] 0 bit 1 r/w f1[1] 0 bit 0 r/w f1[0] 0 f1[7:0] the f1[7:0] bits contain the value inserted in the path user channel octet (f1). f1[7] is the most significant bit, and is transmitted first. f1[0] is the least significant bit and is the last bit transmitted in the octet.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 114 document id: pmc-1990267, issue 3 register 310h: change of pmon performance meters bit type function default bit 7 unused x bit 6 unused x bit 5 r lcvch x bit 4 r ferrch x bit 3 r exzs x bit 2 r perrch x bit 1 r cperrch x bit 0 r febech x febech the febech bit is set to logic one if one or more febe events (or j2 exzs events when the j2 framing format is selected) have occurred during the latest pmon accumulation interval. cperrch the cperrch bit is set to logic one if one or more path parity error events have occurred during the latest pmon accumulation interval. perrch the perrch bit is set to logic one if one or more parity error events (or j2 crc-5 errors) have occurred during the latest pmon accumulation interval. exzs the exzs bit is set to logic one if one or more summed lcv events in ds3 mode have occurred during the latest pmon accumulation interval. ferrch the ferrch bit is set to logic one if one or more f-bit or m-bit error events have occurred during the latest pmon accumulation interval. lcvch the lcvch bit is set to logic one if one or more lcv events have occurred during the latest pmon accumulation interval.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 115 document id: pmc-1990267, issue 3 register 311h: pmon interrupt enable/status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w inte 0 bit 1 r intr x bit 0 r ovr x ovr the ovr bit indicates the overrun status of the pmon holding registers. a logic one in this bit position indicates that a previous interrupt has not been cleared before the end of the next accumulation interval, and that the contents of the holding registers have been overwritten. a logic zero indicates that no overrun has occurred. this bit is reset to logic zero when this register is read. intr the intr bit indicates the current status of the interrupt signal. a logic one in this bit position indicates that a transfer of counter values to the holding registers has occurred; a logic zero indicates that no transfer has occurred. the intr bit is set to logic zero when this register is read. inte the inte bit enables the generation of an interrupt when the pmon counter values are transferred to the holding registers. when a logic one is written to inte, the interrupt generation is enabled.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 116 document id: pmc-1990267, issue 3 register 314h: pmon lcv event count lsb bit type function default bit 7 r lcv[7] x bit 6 r lcv[6] x bit 5 r lcv[5] x bit 4 r lcv[4] x bit 3 r lcv[3] x bit 2 r lcv[2] x bit 1 r lcv[1] x bit 0 r lcv[0] x register 315h: pmon lcv event count msb bit type function default bit 7 r lcv[15] x bit 6 r lcv[14] x bit 5 r lcv[13] x bit 4 r lcv[12] x bit 3 r lcv[11] x bit 2 r lcv[10] x bit 1 r lcv[9] x bit 0 r lcv[8] x lcv[15:0] lcv[15:0] represents the number of ds3, e3, or j2 lcv errors that have been detected since the last time the lcv counter was polled. the counter (and all other counters in the pmon) is polled by writing to any of the pmon register addresses (314h to 31fh) or to the s/uni-jet identification, master reset, and global monitor update register (006h). such a write transfers the internally accumulated count to the lcv error count registers and simultaneously resets the internal counter to begin a new cycle of error accumulation. this transfer and reset is carried out in a manner that coincident events are not lost. the transfer takes three rclk cycles to complete.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 117 document id: pmc-1990267, issue 3 register 316h: pmon framing bit error event count lsb bit type function default bit 7 r ferr[7] x bit 6 r ferr[6] x bit 5 r ferr[5] x bit 4 r ferr[4] x bit 3 r ferr[3] x bit 2 r ferr[2] x bit 1 r ferr[1] x bit 0 r ferr[0] x 317h: pmon framing bit error event count msb bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r ferr[9] x bit 0 r ferr[8] x ferr[9:0] ferr[9:0] represents the number of ds3 f-bit and m-bit errors, or e3 or j2 framing pattern errors, that have been detected since the last time the framing error counter was polled. the counter (and all other counters in the pmon) is polled by writing to any of the pmon register addresses (314h to 31fh) or to the s/uni-jet identification, master reset, and global monitor update register (006h). such a write transfers the internally accumulated count to the ferr error event count registers and simultaneously resets the internal counter to begin a new cycle of error accumulation. this transfer and reset is carried out in a manner that coincident events are not lost. the transfer takes 255 rclk cycles to complete in ds3 mode and three rclk cycles to complete in e3 and j2 mode. this counter is paused when the corresponding framer has lost frame alignment.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 118 document id: pmc-1990267, issue 3 register 318h: pmon excessive zero count lsb bit type function default bit 7 r exzs[7] x bit 6 r exzs[6] x bit 5 r exzs[5] x bit 4 r exzs[4] x bit 3 r exzs[3] x bit 2 r exzs[2] x bit 1 r exzs[1] x bit 0 r exzs[0] x register 319h: pmon excessive zero count msb bit type function default bit 7 r exzs[15] x bit 6 r exzs[14] x bit 5 r exzs[13] x bit 4 r exzs[12] x bit 3 r exzs[11] x bit 2 r exzs[10] x bit 1 r exzs[9] x bit 0 r exzs[8] x exzs[15:0] in ds3 mode, exzs[15:0] represents the number of summed excessive zeros (exzs) that occurred during the previous accumulation interval. one or more excessive zeros occurrences within an 85 bit ds3 information block is counted as one summed excessive zero. excessive zeros are accumulated by this register only when the exzso and exzdet are logic one in the ds3 frmr additional configuration register. this register accumulates summed lcv when the exzso is logic zero. the count of summed lcv is defined as the number of ds3 information blocks (85 bits) that contain one or more lcv since the last time the summed lcv counter was polled. the counter (and all other counters in the pmon) is polled by writing to any of the pmon register addresses (314h to 31fh) or to the s/uni-jet identification, master reset, and global monitor update register (006h). such a write transfers the internally accumulated count to the exzs event count registers and simultaneously resets the internal counter to begin a new cycle of error accumulation. this transfer and reset is carried out in a manner that coincident events are not lost. the transfer takes 255 rclk cycles to complete in ds3 mode and a maximum of 500 rclk cycles to complete in g.832 e3 mode.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 119 document id: pmc-1990267, issue 3 register 31ah: pmon parity error event count lsb bit type function default bit 7 r perr[7] x bit 6 r perr[6] x bit 5 r perr[5] x bit 4 r perr[4] x bit 3 r perr[3] x bit 2 r perr[2] x bit 1 r perr[1] x bit 0 r perr[0] x register 31bh: pmon parity error event count msb bit type function default bit 7 r perr[15] x bit 6 r perr[14] x bit 5 r perr[13] x bit 4 r perr[12] x bit 3 r perr[11] x bit 2 r perr[10] x bit 1 r perr[9] x bit 0 r perr[8] x perr[15:0] perr[15:0] represents the number of ds3 p-bit errors, the number of e3 g.832 bip-8 errors or the number of j2 crc-5 errors that have been detected since the last time the parity error counter was polled. the counter (and all other counters in the pmon) is polled by writing to any of the pmon register addresses (314h to 31fh) or to the s/uni-jet identification, master reset, and global monitor update register (006h). such a write transfers the internally accumulated count to the perr error count registers and simultaneously resets the internal counter to begin a new cycle of error accumulation. this transfer and reset is carried out in a manner that coincident events are not lost. the transfer takes 255 rclk cycles to complete in ds3 mode and three rclk cycles to complete in e3 and j2 mode. this counter is paused when the corresponding framer has lost frame alignment.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 120 document id: pmc-1990267, issue 3 register 31ch: pmon path parity error event count lsb bit type function default bit 7 r cperr[7] x bit 6 r cperr[6] x bit 5 r cperr[5] x bit 4 r cperr[4] x bit 3 r cperr[3] x bit 2 r cperr[2] x bit 1 r cperr[1] x bit 0 r cperr[0] x register 31dh: pmon path parity error event count msb bit type function default bit 7 unused x bit 6 unused x bit 5 r cperr[13] x bit 4 r cperr[12] x bit 3 r cperr[11] x bit 2 r cperr[10] x bit 1 r cperr[9] x bit 0 r cperr[8] x cperr[13:0] when configured for ds3 applications, cperr[13:0] represents the number of ds3 path parity errors that have been detected since the last time the ds3 path parity error counter was polled. this counter is forced to zero when the s/uni-jet is configured for either j2 and e3 applications. the counter (and all other counters in the pmon) is polled by writing to any of the pmon register addresses (314h to 31fh) or to the s/uni-jet identification, master reset, and global monitor update register (006h). such a write transfers the internally accumulated count to the cperr error count registers and simultaneously resets the internal counter to begin a new cycle of error accumulation. this transfer and reset is carried out in a manner that coincident events are not lost. the transfer takes 255 rclk cycles to complete. this counter is paused when the corresponding framer has lost frame alignment.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 121 document id: pmc-1990267, issue 3 register 31eh: pmon febe/j2-exzs event count lsb bit type function default bit 7 r febe/j2-exzs[7] x bit 6 r febe/j2-exzs[6] x bit 5 r febe/j2-exzs[5] x bit 4 r febe/j2-exzs[4] x bit 3 r febe/j2-exzs[3] x bit 2 r febe/j2-exzs[2] x bit 1 r febe/j2-exzs[1] x bit 0 r febe/j2-exzs[0] x register 31fh: pmon febe/j2-exzs event count msb bit type function default bit 7 unused x bit 6 unused x bit 5 r febe/j2-exzs[13] x bit 4 r febe/j2-exzs[12] x bit 3 r febe/j2-exzs[11] x bit 2 r febe/j2-exzs[10] x bit 1 r febe/j2-exzs[9] x bit 0 r febe/j2-exzs[8] x febe/j2-exzs[13:0] febe/j2-exzs[13:0] represents the number of ds3 or e3 g.832 febes that have been detected since the last time the febe error counter was polled. in j2 mode, febe/j2-exzs[13:0] represents the number of excessive zeros (exzs is a string of eight or more consecutive zeros) that have occurred during the previous accumulation interval. the counter (and all other counters in the pmon) is polled by writing to any of the pmon register addresses (314h to 31fh) or to the s/uni-jet identification, master reset, and global monitor update register (006h). such a write transfers the internally accumulated count to the febe event count registers and simultaneously resets the internal counter to begin a new cycle of error accumulation. this transfer and reset is carried out in a manner that coincident events are not lost. the transfer takes 255 rclk cycles to complete in ds3 mode and three rclk cycles to complete in e3 and j2 mode.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 122 document id: pmc-1990267, issue 3 register 321h: cppm change of cppm performance meters bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r febech x bit 1 r fech x bit 0 r bipech x bipech the bipech bit is set to logic one if one or more plcp bit interleaved parity error events have occurred since the last cppm accumulation interval. fech the fech bit is set to logic one if one or more plcp frame alignment pattern octet errors, or path overhead identification octet errors have occurred since the last cppm accumulation interval. febech the febech bit is set to logic one if one or more plcp febe events have occurred since the last cppm accumulation interval.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 123 document id: pmc-1990267, issue 3 register 322h: cppm b1 error count lsb bit type function default bit 7 r b1e[7] x bit 6 r b1e[6] x bit 5 r b1e[5] x bit 4 r b1e[4] x bit 3 r b1e[3] x bit 2 r b1e[2] x bit 1 r b1e[1] x bit 0 r b1e[0] x register 323h: cppm b1 error count msb bit type function default bit 7 r b1e[15] x bit 6 r b1e[14] x bit 5 r b1e[13] x bit 4 r b1e[12] x bit 3 r b1e[11] x bit 2 r b1e[10] x bit 1 r b1e[9] x bit 0 r b1e[8] x b1e[15:0] b1e[15:0] represents the number of plcp bit interleaved parity (bip) errors that have been detected since the last time the b1 error counter was polled. the counter (and all other counters in the cppm) is polled by writing to any of the cppm register addresses (322h ? 32fh). such a write transfers the internally accumulated count to the b1 error count registers and simultaneously resets the internal counter to begin a new cycle of error accumulation. this transfer occurs within 67 rclk periods (1.5 s for the ds3 bit rate; 1.95s for the e3 bit rate) of the write. the transfer and reset is carried out in a manner that coincident events are not lost. b1 errors are not accumulated when the s/uni-jet has declared a plcp lof defect state.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 124 document id: pmc-1990267, issue 3 register 324h: cppm framing error event count lsb bit type function default bit 7 r fe[7] x bit 6 r fe[6] x bit 5 r fe[5] x bit 4 r fe[4] x bit 3 r fe[3] x bit 2 r fe[2] x bit 1 r fe[1] x bit 0 r fe[0] x register 325h: cppm framing error event count msb bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r fe[11] x bit 2 r fe[10] x bit 1 r fe[9] x bit 0 r fe[8] x fe[11:0] fe[11:0] represents the number of plcp framing pattern octet errors and path overhead identification octet errors that have been detected since the last time the framing error event counter was polled. the counter (and all other counters in the cppm) is polled by writing to any of the cppm register addresses (322h ? 32fh). such a write transfers the internally accumulated count to the framing error event count registers and simultaneously resets the internal counter to begin a new cycle of error accumulation. this transfer occurs within 67 rclk periods (1.5 s for the ds3 bit rate; 1.95s for the e3 bit rate) of the write. the transfer and reset is carried out in a manner that coincident events are not lost. framing error errors are not accumulated when the s/uni-jet has declared a plcp lof defect state.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 125 document id: pmc-1990267, issue 3 register 326h: cppm febe count lsb bit type function default bit 7 r febe[7] x bit 6 r febe[6] x bit 5 r febe[5] x bit 4 r febe[4] x bit 3 r febe[3] x bit 2 r febe[2] x bit 1 r febe[1] x bit 0 r febe[0] x register 327h: cppm febe count msb bit type function default bit 7 r febe[15] x bit 6 r febe[14] x bit 5 r febe[13] x bit 4 r febe[12] x bit 3 r febe[11] x bit 2 r febe[10] x bit 1 r febe[9] x bit 0 r febe[8] x febe[15:0] febe[15:0] represents the number of plcp febes (febe) that have been detected since the last time the febe error counter was polled. the counter (and all other counters in the cppm) is polled by writing to any of the cppm register addresses (322h ? 32fh). such a write transfers the internally accumulated count to the febe error count registers and simultaneously resets the internal counter to begin a new cycle of error accumulation. this transfer occurs within 67 rclk periods (1.5 s for the ds3 bit rate; 1.95s for the e3 bit rate) of the write. the transfer and reset is carried out in a manner that coincident events are not lost. febe errors are not accumulated when the s/uni-jet has declared a plcp lof defect state.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 126 document id: pmc-1990267, issue 3 register 330h: ds3 frmr configuration bit type function default bit 7 r/w aispat 1 bit 6 r/w fdet 0 bit 5 r/w mbdis 0 bit 4 r/w m3o8 0 bit 3 r/w uni 0 bit 2 r/w refr 0 bit 1 r/w aisc 0 bit 0 r/w cbe 0 cbe the cbe bit enables the ds3 c-bit parity application. when a logic one is written to cbe, c- bit parity mode is enabled. when a logic zero is written to cbe, the ds3 m23 format is selected. while the c-bit parity application is enabled, c-bit parity error events, febes are accumulated. aisc the aisc bit controls the algorithm used to detect the ais (ais). when a logic one is written to aisc, the algorithm checks that a framed ds3 signal with all c-bits set to logic zero is observed for a period of time before declaring ais. the payload contents are checked to the pattern selected by the aispat bit. when a logic zero is written to aisc, the ais detection algorithm is determined solely by the settings of aispat and aisones register bits (see bit mapping table in the additional configuration register description). refr the refr bit initiates a ds3 reframe. when a logic one is written to refr, the s/uni-jet is forced oof, and a new search for frame alignment is initiated. note: only a low-to-high transition of the refr bit triggers reframing; multiple write operations are required to ensure such a transition. uni the uni bit configures the s/uni-jet to accept either dual-rail or single-rail receive ds3 streams. when a logic one is written to uni, the s/uni-jet accepts a single-rail ds3 stream on rdati. the s/uni-jet accumulates lcv on the rlcv input. when a logic zero is written to uni, the s/uni-jet accepts b3zs-encoded dual-rail data on rpos and rneg.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 127 document id: pmc-1990267, issue 3 m3o8 the m3o8 bit controls the ds3 oof decision criteria. when a logic one is written to m3o8, ds3 oof is declared when three of eight framing bits (f-bits) are in error. when a logic zero is written to m3o8, the three of 16 framing bits in error criteria is used, as recommended in ansi t1.107 mbdis the mbdis bit disables the use of m-bit errors as a criteria for losing frame alignment. when mbdis is set to logic one, m-bit errors are disabled from causing an oof; the lof criteria is based solely on the number of f-bit errors selected by the m3o8 bit. when mbdis is set to logic zero, errors in either m-bits or f-bits are enabled to cause an oof. when mbdis is logic zero, an oof can occur when one or more m-bit errors occur in three out of 4 consecutive m-frames, or when the f-bit error ratio selected by the m3o8 bit is exceeded. fdet the fdet bit selects the fast detection timing for ais, idle and red. when fdet is set to logic one, the ais, idle, and red detection time is 2.23 ms; when fdet is set to logic zero, the detection time is 13.5 ms. aispat the aispat bit controls the pattern used to detect the ais (ais). when a logic one is written to aispat, the ais detection algorithm checks that a framed ds3 signal containing the repeating pattern 1010.. is present. the c-bits are checked for the value specified by the aisc bit setting. when a logic zero is written to aispat, the ais detection algorithm is determined solely by the settings of aisc and aisones register bits (see bit mapping table in the additional configuration register description).
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 128 document id: pmc-1990267, issue 3 register 331h: ds3 frmr interrupt enable (ace=0) bit type function default bit 7 r/w cofae 0 bit 6 r/w rede 0 bit 5 r/w cbite 0 bit 4 r/w ferfe 0 bit 3 r/w idle 0 bit 2 r/w aise 0 bit 1 r/w oofe 0 bit 0 r/w lose 0 lose the lose bit enables interrupt generation when a ds3 losdefect is declared or removed. the interrupt is enabled when a logic one is written. oofe the oofe bit enables interrupt generation when a ds3 oof defect is declared or removed. the interrupt is enabled when a logic one is written. aise the aise bit enables interrupt generation when the ds3 ais maintenance signal is detected or removed. the interrupt is enabled when a logic one is written. idle the idle bit enables interrupt generation when the ds3 idle maintenance signal is detected or removed. the interrupt is enabled when a logic one is written. ferfe the ferfe bit enables interrupt generation when a ds3 far end receive failure defect is declared or removed. the interrupt is enabled when a logic one is written. cbite the cbite bit enables interrupt generation when the s/uni-jet detects a change of state in the ds3 application identification channel. the interrupt is enabled when a logic one is written.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 129 document id: pmc-1990267, issue 3 rede the rede bit enables an interrupt to be generated when a change of state of the ds3 red indication occurs. the ds3 red indication is visible in the redv bit location of the ds3 frmr status register. when rede is set to logic one, the interrupt output, intb, is set low when the state of the red indication changes. cofae the cofae bit enables interrupt generation when the s/uni-jet detects a ds3 change of frame alignment. the interrupt is enabled when a logic one is written.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 130 document id: pmc-1990267, issue 3 register 331h: ds3 frmr additional configuration register (ace=1 in register 333h) bit type function default bit 7 unused x bit 6 unused x bit 5 r/w aisones 0 bit 4 r/w bpvo 0 bit 3 r/w exzso 0 bit 2 r/w exzdet 0 bit 1 r/w salgo 0 bit 0 r/w dalgo 0 dalgo the dalgo bit determines the criteria used to decode a valid b3zs signature. when dalgo is set to logic one, a valid b3zs signature is declared and three zeros substituted whenever a zero followed by a bipolar violation of the opposite polarity to the last observed bpv is seen. when the dalgo bit is set to logic zero, a valid b3zs signature is declared and the three zeros are substituted whenever a zero followed by a bipolar violation is observed. salgo the salgo bit determines the criteria used to establish a valid b3zs signature used to map bpvs to lcv indications. any bpv that is not part of a valid b3zs signature is indicated as an lcv. when the salgo bit is set to logic one, a valid b3zs signature is declared whenever a zero followed by a bipolar violation is observed. when salgo is set to logic zero, a valid b3zs signature is declared whenever a zero followed by a bipolar violation of the opposite polarity to the last observed bpv is seen. exzdet the exzdet bit determines the type of zero occurrences to be included in the lcv indication. when exzdet is set to logic one, the occurrence of an excessive zero generates a single pulse indication that is used to indicate an lcv. when exzdet is set to logic zero, every occurrence of three consecutive zeros generates a pulse indication that is used to indicate an lcv. for example, if a sequence of 15 consecutive zeros were received, with exzdet=1 only a single lcv would be indicated for this string of excessive zeros; with exzdet=0, five lcvs would be indicated for this string (i.e. one lcv for every three consecutive zeros). refer to table 14.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 131 document id: pmc-1990267, issue 3 exzso the exzso bit enables only summed zero occurrences to be accumulated in the pmon exzs count registers. when exzso is set to logic one, any excessive zeros occurrences over an 85 bit period increments the pmon exzs counter by one. when exzso is set to logic zero, summed lcvs are accumulated in the pmon exzs count registers. a summed lcv is defined as the occurrence of either bpvs not part of a valid b3zs signature or three consecutive zeros (or excessive zeros if exzdet=1) occurring over an 85 bit period; each summed lcv occurrence increment the pmon exzs counter by one. refer to table 14. bpvo the bpvo bit enables only bipolar violations to indicate lcv and be accumulated in the pmon lcv count registers. when bpvo is set to logic one, only bpvs not part of a valid b3zs signature generate an lcv indication and increment the pmon lcv counter. when bpvo is set to logic zero, both bpvs not part of a valid b3zs signature, and either three consecutive zeros or excessive zeros generate an lcv indication and increment the pmon lcv counter. refer to table 14. table 14 ds3 frmr exzs/lcv count configurations register bit counter function exzso bpvo exzdet pmon exz count pmon lcv count 0 0 0 summed lcvs bpvs & every 3 consecutive zeros 0 0 1 summed lcvs bpvs & every string of more than 3 consecutive zeros 0 1 0 reserved reserved 0 1 1 reserved reserved 1 0 0 summed excessive zeros bpvs & every 3 consecutive zeros 101 summed excessive zeros bpvs & every string of 3+ consecutive zeros 110 summed excessive zeros only bpvs 111 summed excessive zeros only bpvs
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 132 document id: pmc-1990267, issue 3 aisones the aisones bit controls the pattern used to detect the ais (ais) when both aispat and aisc bits in ds3 frmr configuration register are logic zero; if either aispat or aisc are logic one, the aisones bit is ignored. when a logic zero is written to aisones, the algorithm checks that a framed all-ones payload pattern (1111..) signal is observed for a period of time before declaring ais. only the payload bits are observed to follow an all-ones pattern, the overhead bits (x, p, m, f, c) are ignored. when a logic one is written to aisones, the algorithm checks that an unframed all-ones pattern (1111..) signal is observed for a period of time before declaring ais. in this case all the bits, including the overhead, are observed to follow an all-ones pattern. the valid combinations of aispat, aisc, and aisones bits are summarized in table 15: table 15 ds3 frmr ais configurations aispat aisc aisones ais detected 1 0 x framed ds3 stream containing repeating 1010? pattern; overhead bits ignored. 0 1 x framed ds3 stream containing c-bits all logic zero; payload bits ignored. 1 1 x framed ds3 stream containing repeating 1010? pattern in the payload, c-bits all logic zero, and x-bits=1. this can be detected by setting both aispat and aisc high, and declaring ais only when aisv=1 and ferfv=0 (register x33h). 0 0 0 framed ds3 stream containing all-ones payload pattern; overhead bits ignored. 0 0 1 unframed all-ones ds3 stream.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 133 document id: pmc-1990267, issue 3 register 332h: ds3 frmr interrupt status bit type function default bit 7 r cofai x bit 6 r redi x bit 5 r cbiti x bit 4 r ferfi x bit 3 r idli x bit 2 r aisi x bit 1 r oofi x bit 0 r losi x losi the losi bit is set to logic one when a los defect is detected or removed. the losi bit position is set to logic zero when this register is read. oofi the oofi bit is set to logic one when an oof defect is detected or removed. the oofi bit position is set to logic zero when this register is read. aisi the aisi bit is set to logic one when the ds3 ais maintenance signal is detected or removed. the aisi bit position is set to logic zero when this register is read. idli the idli bit is set to logic one when the ds3 idle maintenance signal is detected or removed. the idli bit position is set to logic zero when this register is read. ferfi the ferfi bit is set to logic one when a ferf defect is detected or removed. the ferfi bit position is set to logic zero when this register is read. cbiti the cbiti bit is set to logic one when a change of state is detected in the ds3 application identification channel. the cbiti bit position is set to logic zero when this register is read.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 134 document id: pmc-1990267, issue 3 redi the redi bit indicates that a change of state of the ds3 red indication has occurred. the ds3 red indication is visible in the redv bit location of the ds3 frmr status register. when the redi bit is a logic one, a change in the red state has occurred. when the redi bit is logic zero, no change in the red state has occurred. cofai the cofai bit is set to logic one when a change of frame alignment is detected. a cofa is generated when a new ds3 frame alignment is determined that differs from the last known frame alignment. the cofai bit position is set to logic zero when this register is read.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 135 document id: pmc-1990267, issue 3 register 333h: ds3 frmr status bit type function default bit 7 r/w ace 0 bit 6 r redv x bit 5 r cbitv x bit 4 r ferfv x bit 3 r idlv x bit 2 r aisv x bit 1 r oofv x bit 0 r losv x losv the losv bit indicates the current los defect state. losv is a logic one when a sequence of 175 zeros is detected on the b3zs encoded ds3 receive stream. losv is a logic zero when a signal with a ones density greater than 33% for 175 1 bit periods is detected. oofv the oofv bit indicates the current ds3 oof defect state. when the s/uni-jet has lost frame alignment and is searching for the new alignment, oofv is set to logic one. when the s/uni-jet has found frame alignment, the oofv bit is set to logic zero. aisv the aisv bit indicates the ais state. when the s/uni-jet detects the ais maintenance signal, aisv is set to logic one. idlv the idlv bit indicates the idle signal state. when the s/uni-jet detects the idle maintenance signal, idlv is set to logic one. ferfv the ferfv bit indicates the current far end receive failure defect state. when the s/uni-jet detects an m-frame with the x1 and x2 bits both set to zero, ferfv is set to logic one. when the s/uni-jet detects an m-frame with the x1 and x2 bits both set to one, ferfv is set to logic zero.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 136 document id: pmc-1990267, issue 3 cbitv the cbitv bit indicates the application identification channel (aic) state. cbitv is set to logic one (indicating the presence of the c-bit parity application) when the aic bit is set high for 63 consecutive m-frames. cbitv is set to logic zero (indicating the presence of the m23 or syntran applications) when aic is set low for 2 or more m-frames in the last 15. redv the redv bit indicates the current state of the ds3 red indication. when the redv bit is a logic one, the ds3 frmr frame alignment acquisition circuitry has been oof for 2.23ms (or for 13.5ms when fdet is logic zero). when the redv bit is logic zero, the frame alignment circuitry has found frame (i.e. oofv=0) for 2.23ms ( or 13.5ms if fdet=0). ace the ace bit selects the additional configuration register. this register is located at address 331h, and is only accessible when the ace bit is set to logic one. when ace is set to logic zero, the interrupt enable register is accessible at address 331h.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 137 document id: pmc-1990267, issue 3 register 334h: ds3 tran configuration bit type function default bit 7 r/w cbtran 0 bit 6 r/w ais 0 bit 5 r/w idl 0 bit 4 r/w ferf 0 bit 3 r/w reserved 0 bit 2 unused x bit 1 unused x bit 0 r/w cbit 0 cbit the cbit bit enables the ds3 c-bit parity application. when cbit is written with a logic one, c-bit parity is enabled, and the s/uni-jet modifies the c-bits as required to include the path maintenance data link, the feac channel, the febe indication, and the path parity. when cbit is written with a logic zero, the m23 application is selected, and each c-bit is set to logic one by the s/uni-jet except for the first c-bit of the frame, which is forced to toggle every frame. note: the c-bits may be modified as required using the ds3 overhead access port (toh) regardless of the setting of this bit. ferf the ferf bit enables insertion of the far end receive failure maintenance signal in the ds3 stream. when ferf is written with a logic one, the x1 and x2 overhead bit positions are set to logic zero. when ferf is written with a logic zero, the x1 and x2 overhead bit positions in the ds3 stream are set to logic one. idl the idl bit enables insertion of the idle maintenance signal in the ds3 stream. when idl is written with a logic one, the ds3 payload is overwritten with the repeating pattern 1100.. the ds3 overhead bit insertion (x, p, m f, and c) continues normally. when idl is written with a logic zero, the idle signal is not inserted. ais the ais bit enables insertion of the ais maintenance signal in the ds3 stream. when ais is written with a logic one, the ds3 payload is overwritten with the repeating pattern 1010.. the ds3 overhead bit insertion (x, p, m and f) continues normally. the values inserted in the c- bits during ais transmission are controlled by the cbtran bit in this register. when ais is written with a logic zero, the ais signal is not inserted.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 138 document id: pmc-1990267, issue 3 cbtran the cbtran bit controls the c-bit values during ais transmission. when cbtran is written with a logic zero, the c-bits are overwritten with zeros during ais transmission as specified in ansi t1.107. when cbtran is written with a logic one, c-bit insertion continues normally (as controlled by the cbit bit in this register) during ais transmission. reserved the reserved bit must be programmed to logic zero for proper operation.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 139 document id: pmc-1990267, issue 3 register 335h: ds3 tran diagnostic bit type function default bit 7 r/w dlos 0 bit 6 r/w dlcv 0 bit 5 unused x bit 4 r/w dferr 0 bit 3 r/w dmerr 0 bit 2 r/w dcperr 0 bit 1 r/w dperr 0 bit 0 r/w dfebe 0 dfebe the dfebe bit controls the insertion of febes in the ds3 stream. when dfebe is written with a logic one, and the c-bit parity application is enabled, the three c-bits in m-subframe 4 are set to a logic zero. when dfebe is written with a logic zero, febes are indicated based on receive framing bit errors and path parity errors. dperr the dperr bit controls the insertion of parity errors (p-bit errors) in the ds3 stream. when dperr is written with a logic one, the p-bits are inverted before insertion. when dperr is written with a logic zero, the parity is calculated and inserted normally. dcperr the dcperr bit controls the insertion of path parity errors in the ds3 stream. when dcperr is written with a logic one and the c-bit parity application is enabled, the three c- bits in m-subframe 3 are inverted before insertion. when dcperr is written with a logic zero, the path parity is calculated and inserted normally. dmerr the dmerr bit controls the insertion of m-bit framing errors in the ds3 stream. when dmerr is written with a logic one, the m-bits are inverted before insertion. when dmerr is written with a logic zero, the m-bits are inserted normally. dferr the dferr bit controls the insertion of f-bit framing errors in the ds3 stream. when dferr is written with a logic one, the f-bits are inverted before insertion. when dferr is written with a logic zero, the f-bits are inserted normally.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 140 document id: pmc-1990267, issue 3 dlcv the dlcv bit controls the insertion of a single lcv in the ds3 stream. when dlcv is written with a logic one, a lcv is inserted by generating an incorrect polarity of violation in the next b3zs signature. the data being transmitted must therefore contain periods of three consecutive zeros in order for the lcv to be inserted. for example, lcv may not be inserted when transmitting ais, but may be inserted when transmitting the idle signal. dlcv is automatically cleared upon insertion of the lcv. dlos the dlos bit controls the insertion of losin the ds3 stream. when dlos is written with a logic one, the data on outputs tpos/tdato and tneg/tohm is forced to continuous zeros.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 141 document id: pmc-1990267, issue 3 register 338h: e3 frmr framing options bit type function default bit 7 unused x bit 6 unused x bit 5 r/w reserved 0 bit 4 r/w uni 0 bit 3 r/w format[1] 0 bit 2 r/w format[0] 0 bit 1 r/w refrdis 0 bit 0 r/w refr 0 refr a transition from logic zero to logic one in the refr bit position forces the e3 framer to initiate a search for frame alignment. the bit must be cleared to logic zero, then set to logic one again to initiate subsequent searches for frame alignment. refrdis the refrdis bit disables reframing under the consecutive framing bit error condition once frame alignment has been found, leaving reframing to be initiated only by software via the refr bit. a logic one in the refrdis bit position causes the frmr to remain "locked in frame" once initial frame alignment has been found. a logic zero allows reframing to occur when four consecutive framing patterns are received in error. format[1:0] the format[1:0] bits determine the framing mode used for pattern matching when finding frame alignment and for generating the output status signals. the format[1:0] bits select one of two framing formats. refer to table 16. table 16 e3 frmr format[1:0] configurations format[1] format[0] framing format selected 0 0 g.751 e3 format 0 1 g.832 e3 format 10reserved 11reserved
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 142 document id: pmc-1990267, issue 3 uni the uni bit selects the mode of the receive data interface. when uni is logic one, the e3- frmr expects unipolar data on the rdati input and accepts lcv indications on the rlcv input. when uni is logic zero, the e3-frmr expects bipolar data on the rpos and rneg inputs and decodes the pulses according to the hdb3 line code. reserved the reserved bit must be programmed to logic zero for proper operation.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 143 document id: pmc-1990267, issue 3 register 339h: e3 frmr maintenance options bit type function default bit 7 unused x bit 6 unused x bit 5 r/w wordbip 0 bit 4 r/w reserved 0 bit 3 r/w worderr 0 bit 2 r/w pyld&just 0 bit 1 r/w ferfdet 0 bit 0 r/w tmarkdet 0 tmarkdet the tmarkdet bit determines the persistency check performed on the timing marker bit (bit 8 of the g.832 maintenance and adaptation byte). when tmarkdet is logic one, the timing marker bit must be in the same state for 5 consecutive frames before the timemk status is changed to that state. when tmarkdet is logic zero, the timing marker bit must be in the same state for three consecutive frames. when a framing mode other than g.832 is selected, the setting of the tmarkdet bit is ignored. ferfdet the ferfdet bit determines the persistency check performed on the far end receive failure (ferf) bit (bit 1 of the g.832 maintenance and adaptation byte) or on the rai (rai) bit (bit 11 of the frame in g.751 mode). when ferfdet is logic one, the ferf, or rai, bit must be in the same state for 5 consecutive frames before the ferf/rai status is changed to that state. when ferfdet is logic zero, the ferf, or rai, bit must be in the same state for three consecutive frames. pyld&just the pyld&just bit selects whether the justification service bits and the tributary justification bits in framing mode g.751 is indicated as overhead or payload. when pyld&just is logic one, the justification service bits and the tributary justification bits are indicated as payload to the splr. when pyld&just is logic zero, the justification service and tributary justification bits are indicated as overhead to splr. for g.751 atm applications, this bit must be set to logic one for correct cell mapping.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 144 document id: pmc-1990267, issue 3 worderr the worderr bit selects whether the framing bit error indication pulses accumulated in pmon indicate all bit errors in the framing pattern or only one error for one or more errors in the framing pattern. when worderr is logic one, the ferr indication to pmon pulses once per frame, accumulating one error for one or more framing bit errors occurred. when worderr is logic zero, the ferr indication to pmon pulses for each and every framing bit error that occurs; pmon accumulates all framing bit errors. reserved the reserved bit must be set to logic zero for proper operation. wordbip the wordbip bit selects whether the parity bit error indication pulses to the e3-tran block indicate all bit errors in the bip-8 pattern or only one error for one or more errors in the bip-8 pattern. when wordbip is logic one, the parity error indication to the e3 tran block pulses once per frame, indicating that one or more parity bit errors occurred. when wordbip is logic zero, the parity error indication to the e3-tran block pulses for each and every parity bit error that occurs. for g.832 applications, this bit should be set to logic one.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 145 document id: pmc-1990267, issue 3 register 33ah: e3 frmr framing interrupt enable bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r/w czde 0 bit 3 r/w lose 0 bit 2 r/w lcve 0 bit 1 r/w cofae 0 bit 0 r/w oofe 0 oofe the oofe bit is an interrupt enable. when oofe is logic one, a change of state of the oof status generates an interrupt and sets the intb output to logic zero. when oofe is logic zero, changes of state of the oof status are disabled from causing interrupts on the intb output. cofae the cofae bit is an interrupt enable. when cofae is logic one, a change of frame alignment generates an interrupt and sets the intb output to logic zero. when cofae is logic zero, changes of frame alignment are disabled from causing interrupts on the intb output. lcve the lcve bit is an interrupt enable. when lcve is logic one, detection of a lcv generates an interrupt and sets the intb output to logic zero. when lcve is logic zero, occurrences of lcv are disabled from causing interrupts on the intb output. lose the lose bit is an interrupt enable. when lose is logic one, a change of state of the loss- of-signal generates an interrupt and sets the intb output to logic zero. when lose is logic zero, occurrences of loss-of-signal are disabled from causing interrupts on the intb output. czde the czde bit is an interrupt enable. when czde is logic one, detection of four consecutive zeros in the hdb3-encoded stream generates an interrupt and sets the intb output to logic zero. when czde is logic zero, occurrences of consecutive zeros are disabled from causing interrupts on the intb output.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 146 document id: pmc-1990267, issue 3 register 33bh: e3 frmr framing interrupt indication and status bit type function default bit 7 unused x bit 6 r czdi x bit 5 r losi x bit 4 r lcvi x bit 3 r cofai x bit 2 r oofi x bit 1 r los x bit 0 r oof x oof the oof bit indicates the current state of the e3-frmr. when oof is logic one, the e3-frmr is oof alignment and actively searching for the new alignment. while oof is high all status indications and overhead extraction continue with the previous known alignment. when oof is logic zero, the e3-frmr has found a valid frame alignment and is operating in a maintenance mode, indicating framing bit errors, and extracting and processing overhead bits. during reset, oof is set to logic one, but the setting may change prior to the register being read. los the los bit indicates the current state of the loss-of-signal detector. when los is logic one, the e3-frmr has received 32 consecutive rclk cycles with no occurrences of bipolar data on rpos and rneg. when los is logic zero, the frmr is receiving valid bipolar data. when the e3-frmr has declared los, the los indication is set to logic zero (de-asserted) when the e3-frmr has received 32 consecutive rclk cycles containing no occurrences of 4 consecutive zeros. the los bit is forced to logic zero if the uni bit is logic one. during reset, los is set to logic zero, but the setting may change prior to the register being read. oofi a logic one oofi bit indicates a change in the oof status. the oofi bit is cleared to logic zero upon the completion of the register read. when oofi is logic zero, it indicates that no oof state change has occurred since the last time this register was read.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 147 document id: pmc-1990267, issue 3 cofai the cofai bit indicates that a change of frame alignment between the previous alignment and the newly found alignment has occurred. when cofai is logic one, the last high-to-low transition on the oof signal resulted in the new frame alignment differing from the previous one. the cofai bit is cleared to logic zero upon the completion of the register read. when cofai is logic zero, it indicates that no change in frame alignment has occurred when oof went low. lcvi the lcvi bit indicates that a lcv has occurred. when lcvi is logic one, a lcv on the rpos and rneg inputs was detected since the last time this register was read. the lcvi bit is cleared to logic zero upon the completion of the register read. when lcvi is logic zero, it indicates that no lcv was detected since the last register read. when the uni bit in the framing options register is logic one, the lcvi is forced to logic zero. losi the losi bit indicates that a state transition occurred on the los status signal. when losi is logic one, a high-to-low or low-to-high transition occurred on the los status signal since the last time this register was read. the losi bit is cleared to logic zero upon the completion of the register read. when losi is logic zero, it indicates that no state change has occurred on los since the last time this register was read. when the uni bit in the framing options register is logic one, the losi is forced to logic zero. czdi the czdi bit indicates that four consecutive zeros in the hdb3-encoded stream have been detected. czdi is asserted to a logic one, whenever the czd signal is asserted. the czdi bit is cleared to a logic zero upon the completion of the register read. when czdi is logic zero, it indicates that no occurrences of four consecutive zeros was detected since the last register read. when the uni bit in the framing options register is logic one, the czdi indication is forced to logic zero. the interrupt indications within this register work independently from the interrupt enable bits, allowing the microprocessor to poll the register to determine the state of the framer. the indication bits (bits 2,3,4,5,6 of this register) are cleared to logic zero after the register is read; the intb output is also cleared to logic one if the interrupt was generated by any of these five events.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 148 document id: pmc-1990267, issue 3 register 33ch: e3 frmr maintenance event interrupt enable bit type function default bit 7 r/w ferre 0 bit 6 r/w perre 0 bit 5 r/w aisde 0 bit 4 r/w ferfe 0 bit 3 r/w febee 0 bit 2 r/w ptypee 0 bit 1 r/w timemke 0 bit 0 r/w natusee 0 natusee the natusee bit is an interrupt enable. when natusee is logic one, an interrupt is generated on the intb output when the national use bit (bit 12 of the frame in g.751 e3 mode) changes state. when natusee is logic zero, changes in state of the national use bit does not cause an interrupt on intb. timemke the timemke bit is an interrupt enable. when timemke is logic one, an interrupt is generated on the intb output when the timing marker bit (bit 8 of the g.832 maintenance and adaptation byte) changes state after the selected persistency check is applied. when timemke is logic zero, changes in state of the timing marker bit does not cause an interrupt on intb. ptypee the ptypee bit is an interrupt enable. when ptypee is logic one, an interrupt is generated on the intb output when the payload type bits (bits 3,4,5 of the g.832 maintenance and adaptation byte) change state. when ptypee is logic zero, changes in state of the payload type bits does not cause an interrupt on intb. febee the febee bit is an interrupt enable. when febee is logic one, an interrupt is generated on the intb output when the febe indication bit (bit 2 of the g.832 maintenance and adaptation byte) changes state. when febee is logic zero, changes in state of the febe bit does not cause an interrupt on intb.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 149 document id: pmc-1990267, issue 3 ferfe the ferfe bit is an interrupt enable. when ferfe is logic one, an interrupt is generated on the intb output when the far end receive failure indication bit (bit 1 of the g.832 maintenance and adaptation byte), or when the rai bit (bit 11 of the frame in g.751) changes state after the selected persistency check is applied. when ferfe is logic zero, changes in state of the ferf or rai bit does not cause an interrupt on intb. aisde the aisde bit is an interrupt enable. when aisde is logic one, an interrupt is generated on the intb output when the aisd indication changes state. when aisde is logic zero, changes in state of the aisd signal does not cause an interrupt on intb. perre the perre bit is an interrupt enable. when perre is logic one, an interrupt is generated on the intb output when a bip-8 error (in g.832 mode) is detected. when perre is logic zero, occurrences of bip-8 errors do not cause an interrupt on intb. ferre the ferre bit is an interrupt enable. when ferre is logic one, an interrupt is generated on the intb output when a framing bit error is detected. when ferre is logic zero, occurrences of framing bit errors do not cause an interrupt on intb.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 150 document id: pmc-1990267, issue 3 register 33dh: e3 frmr maintenance event interrupt indication bit type functioln defaut bit 7 r ferri 0 bit 6 r perri 0 bit 5 r aisdi 0 bit 4 r ferfi 0 bit 3 r febei 0 bit 2 r ptypei 0 bit 1 r timemki 0 bit 0 r natusei 0 natusei the natusei bit is a transition indication. when natusei is logic one, a change of state of the national use bit (bit 12 of the frame in g.751 e3 mode) has occurred. when natusei is logic zero, no change of state of the national use bit has occurred since the last time this register was read. timemki the timemki bit is a transition indication. when timemki is logic one, a change in state of the timing marker bit (bit 8 of the g.832 maintenance and adaptation byte) has occurred. when timemki is logic zero, no changes in the state of the timing marker bit occurred since the last time this register was read. ptypei the ptypei bit is a transition indication. when ptypei is logic one, a change of state of the payload type bits (bits 3,4,5 of the g.832 maintenance and adaptation byte) has occurred. when ptypei is logic zero, no changes in the state of the payload type bits has occurred since the last time this register was read. febei the febei bit is a transition indication. when febei is logic one, a change of state of the febe indication bit (bit 2 of the g.832 maintenance and adaptation byte) has occurred. when febei is logic zero, no changes in the state of the febe bit has occurred since the last time this register was read.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 151 document id: pmc-1990267, issue 3 ferfi the ferfi bit is a transition indication. when ferfi is logic one, a change of state of the far end receive failure indication bit (bit 1 of the g.832 maintenance and adaptation byte), or when the rai bit (bit 12 of the frame in g.751) has occurred. when ferfi is logic zero, no changes in the state of the ferf or rai bit has occurred since the last time this register was read. aisdi the aisdi bit is a transition indication. when aisdi is logic one, a change in state of the aisd indication has occurred. when aisdi is logic zero, no changes in the state of the aisd signal has occurred since the last time this register was read. perri the perri bit is an event indication. when perri is logic one, the occurrence of one or more bip-8 errors (in g.832 mode) has been detected. when perri is logic zero, no occurrences of bip-8 errors have occurred since the last time this register was read. ferri the ferri bit is an event indication. when ferri is logic one, the occurrence of one or more framing bit error has been detected. when ferri is logic zero, no occurrences of framing bit errors have occurred since the last time this register was read. the transition/event interrupt indications within this register work independently from the interrupt enable bits, allowing the microprocessor to poll the register to determine the activity of the maintenance events. the contents of this register are cleared to logic zero after the register is read; the intb output is also cleared to logic one if the interrupt was generated by any of the maintenance event outputs.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 152 document id: pmc-1990267, issue 3 register 33eh: e3 frmr maintenance event status bit type function default bit 7 r aisd x bit 6 r ferf/rai x bit 5 r febe x bit 4 r ptype[2] x bit 3 r ptype[1] x bit 2 r ptype[0] x bit 1 r timemk x bit 0 r natuse x natuse the natuse bit reflects the state of the extracted national use bit (bit 12 of the frame in g.751 e3 mode). timemk the timemk bit reflects the state of the timing marker bit (bit 8 of the g.832 maintenance and adaptation byte). ptype[2:0] the ptype[2:0] bits reflect the state of the payload type bits (bits 3,4,5 of the g.832 maintenance and adaptation byte). these bits are not latched and should be read 2 or three times in rapid succession to ensure a coherent binary value. febe the febe bit reflects the state of the febe indication bit (bit 2 of the g.832 maintenance and adaptation byte). ferf the ferf bit reflects the value of the far end receive failure indication bit (bit 1 of the g.832 maintenance and adaptation byte), or the value of the rai bit (bit 11 of the frame in g.751) when the value has been the same for either three or 5 consecutive frames.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 153 document id: pmc-1990267, issue 3 aisd the aisd bit reflects the state of the ais detection circuitry. when aisd is logic one, less than eight zeros (in g.832 mode), or less than 5 zeros (in g.751 mode), were detected during one complete frame period while the frmr is oof alignment. when aisd is logic zero, eight or more zeros (in g.832 mode), or 5 or more zeros (in g.751 mode), were detected during one complete frame period, or the frmr has found frame alignment.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 154 document id: pmc-1990267, issue 3 register 340h: e3 tran framing options bit type function default bit 7 unused x bit 6 unused x bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w format[1] 0 bit 0 r/w format[0] 0 format[1:0] the format[1:0] bits determine the framing mode used for framing pattern when generating the formatted output data stream. the format[1:0] bits select one of two framing formats: table 17 e3 tran format[1:0] configurations format[1] format[0] framing format selected 0 0 g.751 e3 format 0 1 g.832 e3 format 10 reserved 11 reserved reserved the reserved bit must be programmed to logic zero for correct operation.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 155 document id: pmc-1990267, issue 3 register 341h: e3 tran status and diagnostic options bit type function default bit 7 unused x bit 6 r/w pyld&just 0 bit 5 r/w cperr 0 bit 4 r/w dferr 0 bit 3 r/w dlcv 0 bit 2 r/w reserved 0 bit 1 r/w tais 0 bit 0 r/w natuse 1 natuse the natuse bit determines the default value of the national use bit inserted into the g.751 e3 frame overhead. the value of the natuse bit is logically ored with the bit collected once per frame from the internal hdlc transmitter (if tnetop is set to logic one). when tnetop is logic zero, the natuse bit controls the value of the national use bit. when natuse is logic one, the national use bit (bit 12 in g.751) is forced to logic one regardless of the bit input from the internal hdlc transmitter or the setting of tnetop. when natuse is logic zero, the national use bit is set to the value sampled from the internal hdlc transmitter if tnetop is logic zero. otherwise, the national use bit will be set to logic zero. if the e3 tran is configured for g.832 mode, this bit is ignored. tais the tais bit enables ais signal transmission. when tais is logic one, the all 1?s ais signal is transmitted. when tais is logic zero, the normal data is transmitted. reserved the reserved bit must be programmed to logic zero for proper operation. dlcv the dlcv bit selects whether a lcv is generated for diagnostic purposes. when dlcv changes from logic zero to logic one, single lcv is generated; in hdb3, the lcv is generated by causing a bipolar violation pulse of the same polarity to the previous bipolar violation. to generate another lcv, the dlcv register bit must be first be written to logic zero and then to logic one again.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 156 document id: pmc-1990267, issue 3 dferr the dferr bit selects whether the framing pattern is corrupted for diagnostic purposes. when dferr is logic one, the framing pattern inserted into the output data stream is inverted. when dferr is logic zero, the unaltered framing pattern inserted into the output data stream. cperr the cperr bit enables continuous generation of bip-8 errors for diagnostic purposes. when cperr is logic one, the calculated bip-8 value is continuously inverted according to the error mask specified by the bip-8 error mask register and inserted into the g.832 em byte. when cperr is logic zero, the calculated bip-8 value is altered only once, according to the error mask specified by the bip-8 error mask register, and inserted into the em byte. pyld&just the pyld&just bit selects whether the justification service bits and the tributary justification bits in framing modes g.751 is indicated as overhead or payload. when pyld&just is logic one, the justification service bits and the tributary justification bits are indicated as payload. when pyld&just is logic zero, the justification service and tributary justification bits are indicated as overhead. for g.751 atm applications, this bit must be set to logic one for correct cell mapping.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 157 document id: pmc-1990267, issue 3 register 342h: e3 tran bip-8 error mask bit type function default bit 7 r/w mbip[7] 0 bit 6 r/w mbip[6] 0 bit 5 r/w mbip[5] 0 bit 4 r/w mbip[4] 0 bit 3 r/w mbip[3] 0 bit 2 r/w mbip[2] 0 bit 1 r/w mbip[1] 0 bit 0 r/w mbip[0] 0 mbip[7:0] the mbip[7:0] bits act as an error mask to cause the transmitter to insert up to eight bip-8 errors. the contents of this register are xored with the calculated bip-8 byte and inserted into the g.832 em byte of the frame. a logic one in any mbip bit position causes that bit position in the em byte to be inverted. writing this register with a mask value causes that mask to be applied only once; if continuous bip-8 errors are desired, the cperr bit in the status and diagnostic options register can be used.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 158 document id: pmc-1990267, issue 3 register 343h: e3 tran maintenance and adaptation options bit type function default bit 7 r/w ferf/rai 0 bit 6 r/w febe 0 bit 5 r/w ptype[2] 0 bit 4 r/w ptype[1] 0 bit 3 r/w ptype[0] 0 bit 2 r/w tumfrm[1] 0 bit 1 r/w tumfrm[0] 0 bit 0 r/w timemk 0 timemk the timemk bit determines the state of the timing marker bit (bit 8 of the g.832 maintenance and adaptation byte). when timemk is set to logic one, the timing marker bit in the ma byte is set to logic one. when timemk is set to logic zero, the timing marker bit in the ma byte is set to logic zero. tumfrm[1:0] the tumfrm[1:0] bits reflect the value to be inserted in the tributary unit multiframe bits (bits 6, and 7 of the g.832 maintenance and adaptation byte). these bits are logically ored with the tumfrm[1:0] overhead signals from the toh input before being inserted in the ma byte. ptype[2:0] the ptype[2:0] bits reflect the value to be inserted in the payload type bits (bits 3,4,5 of the g.832 maintenance and adaptation byte). febe the febe bit reflects the value to be inserted in the febe indication bit (bit 2 of the g.832 maintenance and adaptation byte). the febe bit value is logically ored with the febe indications generated by the frmr for any detected bip-8 errors. when the febe bit is logic one, bit 2 of the g.832 ma byte is set to logic one; when the febe bit is logic zero, any bip-8 error indications from the frmr causes bit 2 of the ma byte to be set to logic one.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 159 document id: pmc-1990267, issue 3 ferf/rai the ferf/rai bit reflects the value to be inserted in the far end receive failure indication bit (bit 1 of the g.832 maintenance and adaptation byte), or the value of the rai bit (bit 11 of the frame in g.751). the ferf/rai bit is logically ored with the los, oof, ais, and lcd indications from the e3 frmr and rxcp-50 when the losen, oofen, aisen, and lcden register bits (in the s/uni-jet data link and ferf/rai control register) are set to logic one respectively. when the or of the two signals is logic one, the ferf or rai bit in the frame is set to logic one; when neither signal is logic one, the ferf or rai bit is set to logic zero.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 160 document id: pmc-1990267, issue 3 register 344h: j2-frmr configuration bit type function default bit 7 unused x bit 6 r/w uni 0 bit 5 r/w reframe 0 bit 4 r/w flock 0 bit 3 r/w crc_refr 0 bit 2 r/w sfrme 0 bit 1 r/w losthr[1] 1 bit 0 r/w losthr[0] 1 uni when the uni bit is set to logic zero, the j2-frmr expects unipolar data on the rdati input and lcv indications on the rlcv input. when uni is logic zero, the j2-frmr expects bipolar b8zs encoded data on the rpos and rneg inputs. when uni is set to logic one, then the los, losi, and exzi indications cannot be used. reframe writing the reframe bit logic one forces the j2-frmr to declare lof, and begin searching for a new alignment. in order to force another reframe, reframe must be written with logic zero, and then logic one again. flock when the flock bit is set to logic one, the j2-frmr is prevented from declaring lof and searching for a new frame alignment due to framing-pattern errors. in this case, the j2-frmr will only search for frame alignment when the reframe register bit transitions from logic zero to logic one. crc_refr when the crc reframe enable bit is set to logic one, an alternate framing algorithm is enabled, which uses the crc-5 check to detect framing to a mimic pattern in the payload or signaling bits. the framer, once it has seen at least one correct framing pattern, begins looking for correct crc-5s as well. if it observes three consecutive correct framing patterns, and two correct crc-5 sequences, then frame is declared. otherwise, a reframe is initiated. when crc_refr is set to logic zero, the framing algorithm simply searches for three consecutive correct framing patterns.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 161 document id: pmc-1990267, issue 3 sfrme when the single framing bit error (sfrme) bit is set to logic one, then the j2-frmr will indicate (to the pmon) a single framing error for every j2 multi-frame which contains one or more framing errors. when the sfrme bit is set to logic zero, the j2-frmr will identify every framing error to the pmon. losthr[1:0] the los threshold bits select the number of consecutive zeroes required before the j2- frmr will declare los, and the number of bit periods without an occurrence of excess zeroes that must pass before the j2-frmr will de-assert los. the thresholds are described in table 18: table 18 j2 frmr los threshold configurations losthr[1] losthr[0] threshold 00 15 01 31 10 63 1 1 255 thus, if losthr[1:0] = 11 binary, los will be declared after the 255th consecutive binary zero, and de-asserted when 255 bit periods have passed without an occurrence of a string of eight or more consecutive zeroes.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 162 document id: pmc-1990267, issue 3 register 345h: j2-frmr status bit type function default bit 7 r los x bit 6 r lof x bit 5 unused x bit 4 r rai x bit 3 r rlof x bit 2 unused x bit 1 r phyais x bit 0 r pldais x los, lof, rai, rlof, phyais, pldais these register bits reflect the current state of the los, lof, rai (rai), remote lof (rlof, also known as the a-bit), physical ais (phyais), and payload ais (pldais) conditions.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 163 document id: pmc-1990267, issue 3 register 346h: j2-frmr alarm interrupt enable bit type function default bit 7 r/w lose 0 bit 6 r/w lofe 0 bit 5 r/w cofae 0 bit 4 r/w raie 0 bit 3 r/w rlofe 0 bit 2 r/w rlof_thr 1 bit 1 r/w phyaise 0 bit 0 r/w pldaise 0 lose when lose is logic one, the j2-frmr will generate an interrupt when the los condition changes state. note: the los bit is not valid when the uni bit is set in the j2-frmr configuration register. lofe when lofe is logic one, the j2-frmr will generate an interrupt when lof changes state. cofae when cofae is logic one, the j2-frmr will generate an interrupt when a change of frame alignment occurs. raie when raie is logic one, the j2-frmr will generate an interrupt when rai changes state. rlofe when rlofe is logic one, the j2-frmr will generate an interrupt when rlof changes state.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 164 document id: pmc-1990267, issue 3 rlof_thr the rlof threshold bit determines the number of consecutive a-bits that are required for the state of rlof to change. when rlof_thr is logic zero, rlof is asserted when the a-bit has been logic one for three consecutive frames, and de-asserted when the a-bit has been logic zero for three consecutive frames. when rlof_thr is logic one, rlof is asserted when the a-bit has been logic one for five consecutive frames, and de-asserted when the a-bit has been logic zero for five consecutive frames. the default setting is that five consecutive a- bits are required. phyaise when phyaise is logic one, the j2-frmr will generate an interrupt when a change is detected in the physical ais condition. pldaise when pldaise is logic one, the j2-frmr will generate an interrupt when a change is detected in the payload ais condition.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 165 document id: pmc-1990267, issue 3 register 347h: j2-frmr alarm interrupt status bit type function default bit 7 r losi x bit 6 r lofi x bit 5 r cofai x bit 4 r raii x bit 3 r rlofi x bit 2 unused x bit 1 r phyaisi x bit 0 r pldaisi x losi the losi bit is set to logic one if a change occurs in the los condition. losi is cleared when this register is read. lofi the lofi bit is set to logic one if a change occurs in the state of lof. lofi is cleared when this register is read. cofai the cofai bit is set to logic one if a change in frame alignment occurs. cofai is cleared when this register is read. raii the raii bit is set to logic one if a change in the value of rai occurs. raii is cleared when this register is read. rlofi the rlofi bit is set to logic one if a change in the value of rlof occurs. rlofi is cleared when this register is read. phyaisi the phyaisi bit is set to logic one if a change in the condition of phyais occurs. phyaisi is cleared when this register is read.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 166 document id: pmc-1990267, issue 3 pldaisi the pldaisi bit is set to logic one if a change in the condition of pldais occurs. pldaisi is cleared when this register is read.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 167 document id: pmc-1990267, issue 3 register 348h: j2-frmr error/xbit interrupt enable bit type function default bit 7 r/w crcee 0 bit 6 r/w frmee 0 bit 5 r/w bpve 0 bit 4 r/w exze 0 bit 3 r/w xbite 0 bit 2 unused x bit 1 r/w xbit_deb 0 bit 0 r/w xbit_thr 0 crcee when crcee is logic one, the j2-frmr will generate an interrupt if a multiframe fails its crc-5 check. frmee when frmee is logic one, the j2-frmr will generate an interrupt upon the reception of an errored framing bit. bpve when bpve is logic one, the j2-frmr will generate an interrupt upon the reception of a bipolar violation which is not part of a valid b8zs code (when uni is set to logic zero in the j2-frmr configuration register) or on the reception of a logic one on rlcv (when uni is set to logic one). exze when exze is logic one, the j2-frmr will generate an interrupt upon the reception of a string of eight-or-more consecutive zeroes. exze has no effect when uni is set to logic one in the j2-frmr configuration register. xbite when xbite is logic one, the j2-frmr will generate an interrupt when any of the x-bits (x1, x2, x3) change state. because the xbit interrupt is generated when the x-bit indications change, the interrupt is debounced along with them via the xbit_deb and xbit_thr bits.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 168 document id: pmc-1990267, issue 3 xbit_deb when xbit_deb is set to logic zero, the x-bit indications in the j2-frmr error/xbit interrupt status register reflect the most recent value of the x-bits. when xbit_deb is set to logic one, the x-bit indications change value only when an x-bit has maintained its value for three or five consecutive multiframes, depending on the setting of xbit_thr. xbit_thr when xbit_thr is set to logic one, then xbit_thr controls the debouncing threshold of the x-bit indications in the j2-frmr error/xbit interrupt status register. when xbit_thr is logic zero, the threshold is set to three consecutive multiframes; when xbit_thr is logic one, the threshold is set to five consecutive multiframes.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 169 document id: pmc-1990267, issue 3 register 349h: j2-frmr error/xbit interrupt status bit type function default bit 7 r crcei x bit 6 r frmei x bit 5 r bpvi x bit 4 r exzi x bit 3 r xbiti x bit 2 r x3 x bit 1 r x2 x bit 0 r x1 x crcei the crcei bit is set to logic one if a failed crc-5 check occurs. crcei is cleared when this register is read. frmei the frmei bit is set to logic one if an errored framing bit occurs. frmei is cleared when this register is read. bpvi the bpvi bit is set to logic one if a bipolar violation that is not part of a valid b8zs code occurs (when uni is logic zero in the j2-frmr configuration register) or if a 0 to 1 transition is detected on rlcv (when uni is logic one). bpvi is cleared when this register is read. exzi the exzi bit is set to logic one upon reception of eight-or-more consecutive zeroes. exzi remains logic zero while uni is set to logic one in the j2_frmr configuration register. exzi is cleared when this register is read. xbiti the xbiti bit is set to logic one if a change in the debounced (if xbit_deb is set to logic one) x-bits (x1, x2, and x3) is detected. xbiti is cleared when this register is read.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 170 document id: pmc-1990267, issue 3 x1, x2, x3 the x1, x2, and x3 bits reflect the most recent (debounced if xbit_deb is set to logic one) value of bits 785, 786, and 787 respectively of frame three of each multiframe. these bits are the spare or ?x-bits?
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 171 document id: pmc-1990267, issue 3 register 34ch: j2-tran configuration bit type function default bit 7 unused x bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w x3set 1 bit 2 r/w x2set 1 bit 1 r/w x1set 1 bit 0 r/w rlof 0 rlof the rlof bit controls the state of the a-bit. when rlof is a logic one, the a-bit is also set to logic one. when rlof is a logic zero, the a-bit is set to logic zero. the a-bit in the transmit stream may also be set to logic one if an lof condition in the j2 frmr is detected and the rblen bit is logic one in the s/uni-jet data link and ferf/rai control register. x1set the x1set bit controls the state of the x1 bit (bit 785 in the third frame of a j2 multiframe). when x1set is a logic one, the x1 bit is set to logic one. when x1set is a logic zero, the x1 bit is set to logic zero. x2set the x2set bit controls the state of the x2 bit (bit 786 in the third frame of a j2 multiframe). when x2set is a logic one, the x2 bit is set to logic one. when x2set is a logic zero, the x2 bit is set to logic zero. x3set the x3set bit controls the state of the x3 bit (bit 787 in the third frame of a j2 multiframe). when x3set is a logic one, the x3 bit is set to logic one. when x3set is a logic zero, the x3 bit is set to logic zero. reserved the reserved register bits should be set to logic zero for proper operation.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 172 document id: pmc-1990267, issue 3 register 34dh: j2-tran diagnostic bit type function default bit 7 unused x bit 6 unused x bit 5 r/w pldais 0 bit 4 r/w phyais 0 bit 3 r/w dcrc 0 bit 2 r/w dlos 0 bit 1 r/w dbpv 0 bit 0 r/w dferr 0 dferr the dferr bit controls the insertion of framing alignment signal errors. when dferr is set to logic one, the framing alignment signal is inverted. when dferr is set to logic zero, the framing alignment signal is not inverted. dbpv the dbpv bit controls the insertion of single bipolar violations. when dbpv bit transitions from 0 to 1, a violation is generated by masking the first violation pulse of a b8zs signature. to generate another violation, this bit must first be written to 0 and then to logic one again. when dbpv is a logic zero, no violation is generated. dlos when set to logic one, the dlos bit forces the unipolar and bipolar outputs of the j2 tran to be all zeros. when dlos is logic zero, the outputs of the j2 tran operate normally. dcrc when set to logic one, a the crc-5 check bits (e 1-5 ) are inverted before transmission. dcrc inverts the e 1-5 bits even if cdis of the j2 tran configuration register is set to logic one. phyais when set to logic one, phyais will cause the j2 tran to transmit an all 1's ais (ais). pldais when set to logic one, pldais will cause the j2 tran to insert all-ones in the payload data bits. when pldais is a logic zero, data is processed normally through the j2 tran.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 173 document id: pmc-1990267, issue 3 register 34eh: j2-tran ts97 signaling bit type function default bit 7 r/w ts97[1] 1 bit 6 r/w ts97[2] 1 bit 5 r/w ts97[3] 1 bit 4 r/w ts97[4] 1 bit 3 r/w ts97[5] 1 bit 2 r/w ts97[6] 1 bit 1 r/w ts97[7] 1 bit 0 r/w ts97[8] 1 ts97[1:8] the ts97[1:8] bits control what is inserted into the j2 timeslot 97 bits. ts97[1] is the first bit of timeslot 97 transmitted.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 174 document id: pmc-1990267, issue 3 register 34fh: j2-tran ts98 signaling bit type function default bit 7 r/w ts98[1] 1 bit 6 r/w ts98[2] 1 bit 5 r/w ts98[3] 1 bit 4 r/w ts98[4] 1 bit 3 r/w ts98[5] 1 bit 2 r/w ts98[6] 1 bit 1 r/w ts98[7] 1 bit 0 r/w ts98[8] 1 ts98[1:8] the ts98[1:8] bits control what is inserted into the j2 timeslot 98 bits. ts98[1] is the first bit of timeslot 98 transmitted.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 175 document id: pmc-1990267, issue 3 register 350h: rdlc configuration bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r/w reserved 0 bit 3 r/w men 0 bit 2 r/w mm 0 bit 1 r/w tr 0 bit 0 r/w en 0 en the en bit controls the overall operation of the rdlc. when en is set to logic one, rdlc is enabled; when set to logic zero, rdlc is disabled. when rdlc is disabled, the rdlc fifo buffer and interrupts are all cleared. when rdlc is enabled, it will immediately begin looking for flags. tr setting the terminate reception (tr) bit to logic one forces the rdlc to immediately terminate the reception of the current data frame, empty the rdlc fifo buffer, clear the interrupts, and begin searching for a new flag sequence. the rdlc handles a terminate reception event in the same manner as it would the toggling of the en bit from logic one to logic zero and back to logic one. thus, the rdlc state machine will begin searching for flags. an interrupt will be generated when the first flag is detected. the tr bit will reset itself to logic zero after the register write operation is completed and a rising and falling edge occurs on the internal datalink clock input. if the rdlc configuration register is read after this time, the tr bit value returned will be logic zero. men setting the match enable (men) bit to logic one enables the detection and storage in the rdlc fifo of only those packets whose first data byte matches either of the bytes written to the primary or secondary match address registers, or the universal all-ones address. when the men bit is logic zero, all packets received are written into the rdlc fifo. mm setting the match mask (mm) bit to logic one ignores the pa[1:0] bits of the primary address match register, the sa[1:0] bits of the secondary address match register, and the two least significant bits of the universal all-ones address when performing the address comparison.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 176 document id: pmc-1990267, issue 3 reserved this register bit should be set to logic zero for proper operation.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 177 document id: pmc-1990267, issue 3 register 351h: rdlc interrupt control bit type function default bit 7 r/w inte 0 bit 6 r/w intc[6] 0 bit 5 r/w intc[5] 0 bit 4 r/w intc[4] 0 bit 3 r/w intc[3] 0 bit 2 r/w intc[2] 0 bit 1 r/w intc[1] 0 bit 0 r/w intc[0] 0 intc[6:0] the intc[6:0] bits control the assertion of fifo fill level set point interrupts. the value of intc[6:0] = ?b0000000 sets the interrupt fifo fill level to 128. inte the interrupt enable bit (inte) must set to logic one to allow the internal interrupt status to be propagated to the intb output. when the inte bit is logic zero the rdlc will not assert intb. the contents of the interrupt control register should only be changed when the en bit in the rdlc configuration register is logic zero. this prevents any erroneous interrupt generation.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 178 document id: pmc-1990267, issue 3 register 352h: rdlc status bit type function default bit 7 r fe x bit 6 r ovr x bit 5 r cols x bit 4 r pkin x bit 3 r pbs[2] x bit 2 r pbs[1] x bit 1 r pbs[0] x bit 0 r intr x consecutive reads of the rdlc status and data registers should not occur at rates greater than 1/10 that of the clock selected by the linesysclk bit of the s/uni-jet miscellaneous register (39bh). intr the interrupt (intr) bit reflects the status of the internal rdlc interrupt. if the inte bit in the rdlc interrupt control register is set to logic one, a rdlc interrupt (intr is a logic one) will cause intb to be asserted low. the intr register bit will be set to logic one when one of the following conditions occurs: ? the number of bytes specified in the rdlc interrupt control register are received on the data link and are written into the fifo. ? rdlc fifo buffer overrun is detected. ? the last byte of a packet is written into the rdlc fifo. ? the last byte of an aborted packet is written into the rdlc fifo. ? transition of receiving all-ones to receiving flags is detected. pbs[2:0] the packet byte status (pbs[2:0]) bits indicate the status of the data last read from the fifo as indicated in table 19: table 19 rdlc pbs[2:0] data status pbs[2:0] data status 000 the data byte read from the fifo is not special. 001 the data byte read from the fifo is the dummy byte that was written into the fifo when the first hdlc flag sequence (01111110) was detected. this indicates that the data link became active.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 179 document id: pmc-1990267, issue 3 pbs[2:0] data status 010 the data byte read from the fifo is the dummy byte that was written into the fifo when the hdlc abort sequence (01111111) was detected. this indicates that the data link became inactive. 011 unused. 100 the data byte read from the fifo is the last byte of a normally terminated packet with no crc error and the packet received had an integer number of bytes. 101 the data byte read from the fifo must be discarded because there was a non-integer number of bytes in the packet. 110 the data byte read from the fifo is the last byte of a normally terminated packet with a crc error. the packet was received in error. 111 the data byte read from the fifo is the last byte of a normally terminated packet with a crc error and a non-integer number of bytes. the packet was received in error. pkin the packet in (pkin) bit is logic one when the last byte of a non-aborted packet is written into the fifo. the pkin bit is cleared to logic zero after the rdlc status register is read. cols the change of link status (cols) bit is set to logic one if the rdlc has detected the hdlc flag sequence (01111110) or hdlc abort sequence (01111111) in the data. this indicates that there has been a change in the data link status. the cols bit is cleared to logic zero by reading this register or by clearing the en bit in the rdlc configuration register. for each change in link status, a byte is written into the fifo. if the cols bit is found to be logic one then the rdlc fifo must be read until empty. the status of the data link is determined by the pbs[2:0] bits associated with the data read from the rdlc fifo. ovr the overrun (ovr) bit is set to logic one when data is written over unread data in the rdlc fifo buffer. this bit is not reset to logic zero until after the status register is read. while the ovr bit is logic one, the rdlc and rdlc fifo buffer are held in the reset state, causing the cols and pkin bits to be reset to logic zero. fe the fifo buffer empty (fe) bit is set to logic one when the last rdlc fifo buffer entry is read. the fe bit goes to logic zero when the fifo is loaded with new data.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 180 document id: pmc-1990267, issue 3 register 353h: rdlc data bit type function default bit 7 r rd[7] x bit 6 r rd[6] x bit 5 r rd[5] x bit 4 r rd[4] x bit 3 r rd[3] x bit 2 r rd[2] x bit 1 r rd[1] x bit 0 r rd[0] x consecutive reads of the rdlc status and data registers should not occur at rates greater than 1/10 that of the clock selected by the linesysclk bit of the s/uni-jet miscellaneous register (39bh). rd[7:0] rd[7:0] contains the received data link information. rd[0] corresponds to the first received bit of the data link message. this register reads from the rdlc 128-byte fifo buffer. if data is available, the fe bit in the fifo input status register is logic zero. when an overrun is detected, an interrupt is generated and the fifo buffer is held cleared until the rdlc status register is read.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 181 document id: pmc-1990267, issue 3 register 354h: rdlc primary address match bit type function default bit 7 r/w pa[7] 1 bit 6 r/w pa[6] 1 bit 5 r/w pa[5] 1 bit 4 r/w pa[4] 1 bit 3 r/w pa[3] 1 bit 2 r/w pa[2] 1 bit 1 r/w pa[1] 1 bit 0 r/w pa[0] 1 pa[7:0] the first byte received after a flag character is compared against the contents of this register. if a match occurs, the packet data, including the matching first byte, is written into the fifo. pa[0] corresponds to the first received bit of the data link message. the mm bit in the configuration register is used mask off pa[1:0] during the address comparison.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 182 document id: pmc-1990267, issue 3 register 355h: rdlc secondary address match bit type function default bit 7 r/w sa[7] 1 bit 6 r/w sa[6] 1 bit 5 r/w sa[5] 1 bit 4 r/w sa[4] 1 bit 3 r/w sa[3] 1 bit 2 r/w sa[2] 1 bit 1 r/w sa[1] 1 bit 0 r/w sa[0] 1 sa[7:0] the first byte received after a flag character is compared against the contents of this register. if a match occurs, the packet data, including the matching first byte, is written into the fifo. sa[0] corresponds to the first received bit data link message. the mm bit in the configuration register is used mask off sa[1:0] during the address comparison.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 183 document id: pmc-1990267, issue 3 register 358h: tdpr configuration bit type function default bit 7 r/w flgshare 1 bit 6 r/w fifoclr 0 bit 5 r/w reserved 0 bit 4 unused x bit 3 r/w eom 0 bit 2 r/w abt 0 bit 1 r/w crc 1 bit 0 r/w en 0 consecutive writes to the tdpr configuration, tdpr interrupt status/udr clear, and tdpr transmit data register and reads of the tdpr interrupt status/udr clear register should not occur at rates greater than 1/8th that of the clock selected by the linesysclk bit of the s/uni- jet miscellaneous register (39bh). en the en bit enables the tdpr functions. when en is set to logic one, the tdpr is enabled and flag sequences are sent until data is written into the tdpr transmit data register. when the en bit is set to logic zero, the tdpr is disabled and an all-ones idle sequence is transmitted on the datalink. crc the crc enable bit controls the generation of the ccitt_crc frame check sequence (fcs). setting the crc bit to logic one enables the ccitt-crc generator and appends the 16-bit fcs to the end of each message. when the crc bit is set to logic zero, the fcs is not appended to the end of the message. the crc type used is the ccitt-crc with generator polynomial x 16 + x 12 + x 5 + 1. the high order bit of the fcs word is transmitted first. abt the abort (abt) bit controls the sending of the seven consecutive-ones hdlc abort code. setting the abt bit to a logic one causes the 01111111 code (the 0 is transmitted first) to be transmitted after the current byte from the tdpr fifo is transmitted. the tdpr fifo is then reset. all data in the tdpr fifo will be lost. aborts are continuously sent and the fifo is held in reset until this bit is reset to a logic zero. at least one abort sequence will be sent when the abt bit transitions from logic zero to logic one.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 184 document id: pmc-1990267, issue 3 eom the eom bit indicates that the last byte of data written in the transmit data register is the end of the present data packet. if the crc bit is set then the 16-bit fcs word is appended to the last data byte transmitted and a continuous stream of flags is generated. the eom bit is automatically cleared upon a write to the tdpr transmit data register. reserved this bit should be set to logic zero for proper operation. fifoclr the fifoclr bit resets the tdpr fifo. when set to logic one, fifoclr will cause the tdpr fifo to be cleared. flgshare the flgshare bit configures the tdpr to share the opening and closing flags between successive frames. if flgshare is logic one, then the opening and closing flags between successive frames are shared. if flgshare is logic zero, then separate closing and opening flags are inserted between successive frames.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 185 document id: pmc-1990267, issue 3 register 359h: tdpr upper transmit threshold bit type function default bit 7 unused x bit 6 r/w uthr[6] 1 bit 5 r/w uthr[5] 0 bit 4 r/w uthr[4] 0 bit 3 r/w uthr[3] 0 bit 2 r/w uthr[2] 0 bit 1 r/w uthr[1] 0 bit 0 r/w uthr[0] 0 uthr[6:0] the uthr[6:0] bits define the tdpr fifo fill level which will automatically cause the bytes stored in the tdpr fifo to be transmitted. once the fill level exceeds the uthr[6:0] value, transmission will begin. transmission will not stop until the last complete packet is transmitted and the tdpr fifo fill level is below uthr[6:0] + 1. the value of uthr[6:0] must always be greater than the value of lint[6:0] unless both values are equal to 00h.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 186 document id: pmc-1990267, issue 3 register 35ah: tdpr lower interrupt threshold bit type function default bit 7 unused x bit 6 r/w lint[6] 0 bit 5 r/w lint[5] 0 bit 4 r/w lint[4] 0 bit 3 r/w lint[3] 0 bit 2 r/w lint[2] 1 bit 1 r/w lint[1] 1 bit 0 r/w lint[0] 1 lint[6:0] the lint[6:0] bits define the tdpr fifo fill level which causes an internal interrupt (lfilli) to be generated. once the tdpr fifo level decrements to empty or to a value less than lint[6:0], lfilli and blfill register bits will be set to logic one. lfilli will cause an interrupt on intb if lfille is set to logic one. the value of lint[6:0] must always be less than the value of uthr[6:0] unless both values are equal to 00h.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 187 document id: pmc-1990267, issue 3 register 35bh: tdpr interrupt enable bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r/w reserved 0 bit 3 r/w fulle 0 bit 2 r/w ovre 0 bit 1 r/w udre 0 bit 0 r/w lfille 0 lfille the lfille enables a transition to logic one on lfilli to generate an interrupt on intb. if lfille is a logic one, a transition to logic one on lfilli will generate an interrupt on intb. if lfille is a logic zero, a transition to logic one on lfilli will not generate an interrupt on intb. udre the udre enables a transition to logic one on udri to generate an interrupt on intb. if udre is a logic one, a transition to logic one on udri will generate an interrupt on intb. if udre is a logic zero, a transition to logic one on udri will not generate an interrupt on intb. ovre the ovre enables a transition to logic one on ovri to generate an interrupt on intb. if ovre is a logic one, a transition to logic one on ovri will generate an interrupt on intb. if ovre is a logic zero, a transition to logic one on ovri will not generate an interrupt on intb. fulle the fulle enables a transition to logic one on fulli to generate an interrupt on intb. if fulle is a logic one, a transition to logic one on fulli will generate an interrupt on intb. if fulle is a logic zero, a transition to logic one on fulli will not generate an interrupt on intb. reserved this bit should be set to logic zero for proper operation.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 188 document id: pmc-1990267, issue 3 register 35ch: tdpr interrupt status/udr clear bit type function default bit 7 unused x bit 6 r full x bit 5 r blfill x bit 4 r unused x bit 3 r fulli x bit 2 r ovri x bit 1 r udri x bit 0 r lfilli x consecutive writes to the tdpr configuration, tdpr interrupt status/udr clear, and tdpr transmit data register and reads of the tdpr interrupt status/udr clear register should not occur at rates greater than 1/8th that of the clock selected by the linesysclk bit of the s/uni- jet miscellaneous register (39bh). lfilli the lfilli bit will transition to logic one when the tdpr fifo level transitions to empty or falls below the value of lint[6:0] programmed in the tdpr lower interrupt threshold register. lfilli will assert intb if it is a logic one and lfille is programmed to logic one. lfilli is cleared when this register is read. udri the udri bit will transition to logic one when the tdpr fifo underruns. that is, the tdpr is in the process of transmitting a packet when it runs out of data to transmit. udri will assert intb if it is a logic one and udre is programmed to logic one. udri is cleared when this register is read. ovri the ovri bit will transition to logic one when the tdpr fifo overruns. that is, the tdpr fifo is already full when another data byte is written to the tdpr transmit data register. ovri will assert intb if it is a logic one and ovre is programmed to logic one. ovri is cleared when this register is read. fulli the fulli bit will transition to logic one when the tdpr fifo is full. fulli will assert intb if it is a logic one and fulle is programmed to logic one. fulli is cleared when this register is read.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 189 document id: pmc-1990267, issue 3 blfill the blfill bit is set to logic one if the current fifo fill level is below the lint[7:0] level or is empty. full the full bit reflects the current condition of the tdpr fifo. if full is a logic one, the tdpr fifo already contains 128-bytes of data and can accept no more.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 190 document id: pmc-1990267, issue 3 register 35dh: tdpr transmit data bit type function default bit 7 r/w td[7] x bit 6 r/w td[6] x bit 5 r/w td[5] x bit 4 r/w td[4] x bit 3 r/w td[3] x bit 2 r/w td[2] x bit 1 r/w td[1] x bit 0 r/w td[0] x consecutive writes to the tdpr configuration, tdpr interrupt status/udr clear, and tdpr transmit data register and reads of the tdpr interrupt status/udr clear register should not occur at rates greater than 1/8th that of the clock selected by the linesysclk bit of the s/uni- jet miscellaneous register (39bh). td[7:0] the td[7:0] bits contain the data to be transmitted on the data link. data written to this register is serialized and transmitted (td[0] is transmitted first).
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 191 document id: pmc-1990267, issue 3 register 360h: rxcp-50 configuration 1 bit type function default bit 7 r/w ddscr 0 bit 6 r/w hdscr 0 bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w hcsadd 1 bit 1 r/w hcsdqdb 0 bit 0 r/w discor 0 discor the discor bit controls the hcs error correction algorithm. when discor is a logic zero, the error correction algorithm is enabled, and single-bit errors detected in the cell header are corrected. when discor is a logic one, the error correction algorithm is disabled, and any error detected in the cell header is treated as an uncorrectable hcs error. hcsdqdb the hcsdqdb bit enables hcs checking for either atm type cells or dqdb type cells. when logic zero, atm type cells are processed by checking all four octets in the header for hcs validation. when logic one, dqdb cells are processed by checking only three of the header octets (octets 2, 3 and 4) for hcs validation. hcsadd the hcsadd bit controls the addition of the coset polynomial, x 6 +x 4 +x 2 +1, to the hcs octet prior to comparison. when hcsadd is a logic one, the polynomial is added, and the resulting hcs is compared. when hcsadd is a logic zero, the polynomial is not added, and the unmodified hcs is compared. hdscr hdscr enables the self-synchronous x 43 + 1 descrambler to continue running through the bytes which should contain the atm cell headers. when hdscr is set to logic zero, the descrambling polynomial will function only over the atm payload bytes. when hdscr is set to logic one, the descrambling polynomial will function over all bytes, including the five atm header bytes. this function is available for use with ppp packets and flags which are scrambled at the source to prevent the generation of "killer" sequences.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 192 document id: pmc-1990267, issue 3 ddscr the ddscr bit controls the descrambling of the cell payload with the polynomial x 43 + 1. when ddscr is set to logic one, cell payload descrambling is disabled. when ddscr is set to logic zero, payload descrambling is enabled.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 193 document id: pmc-1990267, issue 3 register 361h: rxcp-50 configuration 2 bit type function default bit 7 r/w ccdis 0 bit 6 r/w hcspass 0 bit 5 r/w idlepass 0 bit 4 r/w in52 0 bit 3 r/w align[1] 0 bit 2 r/w align[0] 0 bit 1 r/w hcsftr[1] 0 bit 0 r/w hcsftr[0] 0 hcsftr[1:0] the hcs filter bits, hcsftr[1:0] indicate the number of consecutive error-free cells required, while in detection mode, before reverting back to correction mode. refer to table 20. table 20 rxcp-50 hcs filtering configurations hcsftr[1:0] cell acceptance threshold 00 one atm cell with correct hcs before resumption of cell acceptance. this cell is accepted. 01 two atm cells with correct hcs before resumption of cell acceptance. the last cell is accepted. 10 four atm cells with correct hcs before resumption of cell acceptance. the last cell is accepted. 11 eight atm cells with correct hcs before resumption of cell acceptance. the last cell is accepted. align[1:0] align[1:0] configures the rxcp-50 to perform cell delineation based on byte, nibble, or bit wide search algorithms when atm direct mapping is used. cell alignment is relative to overhead bits in the serial input data stream. the align[1:0] bits are valid only if atm direct mapping is used. plcp framing must be disabled. the recommended settings for ds3, e3, and j2 are shown in table 21. table 21 rxcp-50 cell delineation algorithm base align[1:0] cell delineation algorithm base 00 bit 01 nibble (ds3) 10 byte (e3,j2, e1, t1) 11 unused
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 194 document id: pmc-1990267, issue 3 in52 the in52 bit defines the number of bytes contained in incoming cells. when in52 is a logic zero, incoming cells are 53-bytes in length. when in52 is a logic one, incoming cells are 52- bytes in length. in order for atm cell delineation to function properly, incoming cells must be 53-bytes in length including a valid hcs byte. the hcs byte can be stripped off on the utopia side using the ds27_53 register bit. if the s/uni qjet is operating in ppp mode, incoming "cells" may be composed of 52 or 53 bytes without an hcs byte. in this case, the ccdis register bit should be set to disable cell delineation, and the ds27_53 register bit should be set so that it is consistent with in52. idlepass the idlepass bit controls the function of the idle cell filter. when idlepass is written with a logic zero, all cells that match the idle cell header pattern and idle cell header mask are filtered out. when idlepass is a logic one, the idle cell header pattern and mask registers are ignored. the default state of this bit and the bits in the idle cell header mask and idle cell header pattern registers enable the dropping of idle cells. hcspass the hcspass bit controls the dropping of cells based on the detection of an uncorrectable hcs error. when hcspass is a logic zero, cells containing an uncorrectable hcs error are dropped. when hcspass is a logic one, cells are passed to the receive fifo regardless of errors detected in the hcs. additionally, the hcs verification finite state machine never exits the correction mode. regardless of the programming of this bit, cells are always dropped while the cell delineation state machine is in the 'hunt' or 'presync' states unless the ccdis bit in this register is set to logic one. ccdis the ccdis bit can be used to disable all cell filtering and cell delineation. all payload data read by the rxcp-50 is passed into its fifo without the requirement of having to find cell delineation first. if plcp framing is disabled, then alignment of the data read out of the atm interface with respect to the line overhead is set by the align[1:0] bits of this register.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 195 document id: pmc-1990267, issue 3 register 362h: rxcp-50 fifo/utopia control & configuration bit type function default bit 7 r/w rxptyp 0 bit 6 unused x bit 5 r/w rcainv 0 bit 4 r/w rcalevel0 1 bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r/w fiforst 0 fiforst the fiforst bit is used to reset the four-cell receive fifo. when fiforst is set to logic zero, the fifo operates normally. when fiforst is set to logic one, the fifo is immediately emptied and further writes into the fifo are ignored (no incoming atm cells will be stored in the fifo). the fifo remains empty and continues to ignore writes until a logic zero is written to fiforst. see section 12.8 on resetting the receive and transmit fifos. rcalevel0 the rcalevel0 register bit selects the behavior of rca and drca[x] when they de-assert (transition to logic zero if rcainv is logic zero, or transition to logic one if rcainv is logic one) as the receive fifo empties. when rcalevel0 is set to logic one, drca[x] and rca indicates that the receive fifo is empty. rca (and drca[x]), if polled, will de-assert on the rising rfclk edge after payload byte 48 (atm8=1) or payload byte 24 (atm8=0) is output. when rcalevel0 is set to logic zero, drca[x] and rca, if polled, indicates that the receive fifo is near empty. drca[x] and rca, if polled, will de-assert on the rising rfclk edge after payload byte 43 (atm8=1) or payload byte 19 (atm8=0) is output. rcainv the rcainv bit inverts the polarity of the drca[x] and rca output signal. when rcainv is a logic one, the polarity of drca[x] and rca is inverted (drca[x] and rca at logic zero means there is a receive cell available to be read). when rcainv is a logic zero, the polarity of rca and drca[x] is not inverted.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 196 document id: pmc-1990267, issue 3 rxptyp the rxptyp bit selects even or odd parity for output rxprty. when set to logic one, output rxprty is the even parity bit for outputs rdat[15:0]. when rxptyp is set to logic zero, rxprty is the odd parity bit for outputs rdat[15:0].
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 197 document id: pmc-1990267, issue 3 register 363h: rxcp-50 interrupt enables and counter status bit type function default bit 7 r xferi x bit 6 r ovr x bit 5 unused x bit 4 r/w xfere 0 bit 3 r/w oocde 0 bit 2 r/w hcse 0 bit 1 r/w fovre 0 bit 0 r/w lcde 0 lcde the lcde bit enables the generation of an interrupt due to a change in the lcd state. when lcde is set to logic one, the interrupt is enabled. fovre the fovre bit enables the generation of an interrupt due to a fifo overrun error condition. when fovre is set to logic one, the interrupt is enabled. hcse the hcse bit enables the generation of an interrupt due to the detection of a corrected or an uncorrected hcs error. when hcse is set to logic one, the interrupt is enabled. oocde the oocde bit enables the generation of an interrupt due to a change in cell delineation state. when oocde is set to logic one, the interrupt is enabled. xfere the xfere bit enables the generation of an interrupt when an accumulation interval is completed and new values are stored in the rxcp-50 count registers. when xfere is set to logic one, the interrupt is enabled.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 198 document id: pmc-1990267, issue 3 ovr the ovr bit is the overrun status of the rxcp-50 performance monitoring count registers. a logic one in this bit position indicates that a previous transfer (indicated by xferi being logic one) has not been acknowledged before the next accumulation interval has occurred and that the contents of the rxcp-50 count registers have been overwritten. ovr is set to logic zero when this register is read. xferi the xferi bit indicates that a transfer of rxcp-50 performance monitoring count data has occurred. a logic one in this bit position indicates that the rxcp-50 count registers have been updated. this update is initiated by writing to one of the rxcp-50 count register locations or to the s/uni-jet identification, master reset, and global monitor update register. xferi is set to logic zero when this register is read.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 199 document id: pmc-1990267, issue 3 register 364h: rxcp-50 status/interrupt status bit type function default bit 7 r oocdv x bit 6 r lcdv x bit 5 unused x bit 4 r oocdi x bit 3 r chcsi x bit 2 r uhcsi x bit 1 r fovri x bit 0 r lcdi x lcdi the lcdi bit is set high when there is a change in the loss of cell delineation (lcd) state. this bit is reset immediately after a read to this register. fovri the fovri bit is set to logic one when a fifo overrun occurs. this bit is reset immediately after a read to this register. no further fifo overrun indications will occur until the condition which caused the original overrun has cleared. in the case where continuous fifo overruns are occurring, only a single overrun indication (fovri -> ?1?) will be recorded until the overruns cease. uhcsi the uhcsi bit is set high when an uncorrected hcs error is detected. this bit is reset immediately after a read to this register. chcsi the chcsi bit is set high when a corrected hcs error is detected. this bit is reset immediately after a read to this register. oocdi the oocdi bit is set high when the rxcp-50 enters or exits the sync state. the oocdv bit indicates whether the rxcp-50 is in the sync state or not. the oocdi bit is reset immediately after a read to this register.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 200 document id: pmc-1990267, issue 3 lcdv the lcdv bit gives the loss of cell delineation state. when lcd is logic one, an out of cell delineation (ocd) defect has persisted for the number of cells specified in the lcd count threshold register. when lcd is logic zero, no ocd has persisted for the number of cells specified in the lcd count threshold register. the cell time period can be varied by using the lcdc[7:0] register bits in the rxcp-50 lcd count threshold register. oocdv the oocdv bit indicates the cell delineation state. when oocdv is high, the cell delineation state machine is in the 'hunt' or 'presync' states and is hunting for the cell boundaries. when oocdv is low, the cell delineation state machine is in the 'sync' state and cells are passed through the receive fifo.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 201 document id: pmc-1990267, issue 3 register 365h: rxcp-50 lcd count threshold (msb) bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w lcdc[10] 0 bit 1 r/w lcdc[9] 0 bit 0 r/w lcdc[8] 1 register 366h: rxcp-50 lcd count threshold (lsb) bit type function default bit 7 r/w lcdc[7] 0 bit 6 r/w lcdc[6] 1 bit 5 r/w lcdc[5] 1 bit 4 r/w lcdc[4] 0 bit 3 r/w lcdc[3] 1 bit 2 r/w lcdc[2] 0 bit 1 r/w lcdc[1] 0 bit 0 r/w lcdc[0] 0 lcdc[10:0] the lcdc[10:0] bits represent the number of consecutive cell periods the receive cell processor must be out of cell delineation before loss of cell delineation (lcd) is declared. likewise, lcd is not de-asserted until receive cell processor is in cell delineation for the number of cell periods specified by lcdc[10:0]. the default value of lcd[10:0] is 360, which translates to the integration periods shown in table 22. table 22 rxcp-50 lcd integration periods format average cell period default lcd integration period ds3 direct mapping 9.59 s 3.45 ms ds3 plcp 10.42 s 3.75 ms e3 g.751 direct mapping 12.46 s 4.49 ms e3 g.751 plcp 13.89 s 5.00 ms e3 g.832 12.50 s 4.50 ms j2 direct mapping 69.01 s 24.84 ms ds1 direct mapping 276.00 s 99.40 ms
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 202 document id: pmc-1990267, issue 3 format average cell period default lcd integration period ds1 plcp 300.00 us 108.00 ms e1 direct mapping 220.83 s 79.50 ms e1 plcp 237.50 s 85.50 ms
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 203 document id: pmc-1990267, issue 3 register 367h: rxcp-50 idle cell header pattern bit type function default bit 7 r/w gfc[3] 0 bit 6 r/w gfc[2] 0 bit 5 r/w gfc[1] 0 bit 4 r/w gfc[0] 0 bit 3 r/w pti[3] 0 bit 2 r/w pti[2] 0 bit 1 r/w pti[1] 0 bit 0 r/w clp 1 gfc[3:0] the gfc[3:0] bits contain the pattern to match in the first, second, third, and fourth bits of the first octet of the 53-octet cell, in conjunction with the idle cell header mask register. the idlepass bit in the configuration 2 register must be set to logic zero to enable dropping of cells matching this pattern. note: an all-zeros pattern must be present in the vpi and vci fields of the idle or unassigned cell. pti[2:0] the pti[2:0] bits contain the pattern to match in the fifth, sixth, and seventh bits of the fourth octet of the 53-octet cell, in conjunction with the idle cell header mask register. the idlepass bit in the configuration 2 register must be set to logic zero to enable dropping of cells matching this pattern. clp the clp bit contains the pattern to match in the eighth bit of the fourth octet of the 53-octet cell, in conjunction with the match header mask register. the idlepass bit in the configuration 2 register must be set to logic zero to enable dropping of cells matching this pattern.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 204 document id: pmc-1990267, issue 3 register 368h: rxcp-50 idle cell header mask bit type function default bit 7 r/w mgfc[3] 1 bit 6 r/w mgfc[2] 1 bit 5 r/w mgfc[1] 1 bit 4 r/w mgfc[0] 1 bit 3 r/w mpti[2] 1 bit 2 r/w mpti[1] 1 bit 1 r/w mpti[0] 1 bit 0 r/w mclp 1 mgfc[3:0] the mgfc[3:0] bits contain the mask pattern for the first, second, third, and fourth bits of the first octet of the 53-octet cell. this mask is applied to the idle cell header pattern register to select the bits included in the cell filter. a logic one in any bit position enables the corresponding bit in the pattern register to be compared. a logic zero causes the masking of the corresponding bit. mpti[3:0] the mpti[3:0] bits contain the mask pattern for the fifth, sixth, and seventh bits of the fourth octet of the 53-octet cell. this mask is applied to the idle cell header pattern register to select the bits included in the cell filter. a logic one in any bit position enables the corresponding bit in the pattern register to be compared. a logic zero causes the masking of the corresponding bit. mclp the clp bit contains the mask pattern for the eighth bit of the fourth octet of the 53-octet cell. this mask is applied to the idle cell header pattern register to select the bits included in the cell filter. a logic one in this bit position enables the mclp bit in the pattern register to be compared. a logic zero causes the masking of the mclp bit.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 205 document id: pmc-1990267, issue 3 register 369h: rxcp-50 corrected hcs error count bit type function default bit 7 r chcs[7] x bit 6 r chcs[6] x bit 5 r chcs[5] x bit 4 r chcs[4] x bit 3 r chcs[3] x bit 2 r chcs[2] x bit 1 r chcs[1] x bit 0 r chcs[0] x chcs[7:0] the chcs[7:0] bits indicate the number of corrected hcs error events that occurred during the last accumulation interval. the contents of these registers are valid after 24 rclk periods containing cell header or payload data (line or plcp overhead periods do not count) after a transfer is triggered by a write to one of rxcp-50's performance monitor counters (registers 369h ? 371h) or to the s/uni-jet identification, master reset, and global monitor update register (006h).
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 206 document id: pmc-1990267, issue 3 register 36ah: rxcp-50 uncorrected hcs error count bit type function default bit 7 r uhcs[7] x bit 6 r uhcs[6] x bit 5 r uhcs[5] x bit 4 r uhcs[4] x bit 3 r uhcs[3] x bit 2 r uhcs[2] x bit 1 r uhcs[1] x bit 0 r uhcs[0] x uhcs[7:0] the uhcs[7:0] bits indicate the number of uncorrectable hcs error events that occurred during the last accumulation interval. the contents of these registers are valid after 24 rclk periods containing cell header or payload data (line or plcp overhead periods do not count) after a transfer is triggered by a write to one of rxcp-50's performance monitor counters (registers 369h ? 371h) or to the s/uni-jet identification, master reset, and global monitor update register (006h).
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 207 document id: pmc-1990267, issue 3 register 36bh: rxcp-50 receive cell counter (lsb) bit type function default bit 7 r rcell[7] x bit 6 r rcell[6] x bit 5 r rcell[5] x bit 4 r rcell[4] x bit 3 r rcell[3] x bit 2 r rcell[2] x bit 1 r rcell[1] x bit 0 r rcell[0] x register 36ch: rxcp-50 receive cell counter bit type function default bit 7 r rcell[15] x bit 6 r rcell[14] x bit 5 r rcell[13] x bit 4 r rcell[12] x bit 3 r rcell[11] x bit 2 r rcell[10] x bit 1 r rcell[9] x bit 0 r rcell[8] x
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 208 document id: pmc-1990267, issue 3 register 36dh: rxcp-50 receive cell counter (msb) bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r rcell[18] x bit 1 r rcell[17] x bit 0 r rcell[16] x rcell[18:0] the rcell[18:0] bits indicate the number of cells received and written into the receive fifo during the last accumulation interval. cells received and filtered due to hcs errors or idle cell matches are not counted. the counter should be polled every second to avoid saturation. the contents of these registers are valid after 24 rclk periods containing cell header or payload data (line or plcp overhead periods do not count) after a transfer is triggered by a write to one of rxcp-50's performance monitor counters (registers 369h ? 371h) or to the s/uni-jet identification, master reset, and global monitor update register (006h).
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 209 document id: pmc-1990267, issue 3 register 36eh: rxcp-50 idle cell counter (lsb) bit type function default bit 7 r icell[7] x bit 6 r icell[6] x bit 5 r icell[5] x bit 4 r icell[4] x bit 3 r icell[3] x bit 2 r icell[2] x bit 1 r icell[1] x bit 0 r icell[0] x register 36fh: rxcp-50 idle cell counter bit type function default bit 7 r icell[15] x bit 6 r icell[14] x bit 5 r icell[13] x bit 4 r icell[12] x bit 3 r icell[11] x bit 2 r icell[10] x bit 1 r icell[9] x bit 0 r icell[8] x
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 210 document id: pmc-1990267, issue 3 register 370h: rxcp-50 idle cell counter (msb) bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r icell[18] x bit 1 r icell[17] x bit 0 r icell[16] x icell[18:0] the icell[18:0] bits indicate the number of idle cells received during the last accumulation interval. the counter should be polled every second to avoid saturation. the contents of these registers are valid after 24 rclk periods containing cell header or payload data (line or plcp overhead periods do not count) after a transfer is triggered by a write to one of rxcp- 50's performance monitor counters (registers 369h ? 371h) or to the s/uni-jet identification, master reset, and global monitor update register (006h).
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 211 document id: pmc-1990267, issue 3 register 380h: txcp-50 configuration 1 bit type function default bit 7 r/w tptyp 0 bit 6 r/w tcalevel0 0 bit 5 r/w hscr 0 bit 4 r/w hcsdqdb 0 bit 3 r/w hcsb 0 bit 2 r/w hcsadd 1 bit 1 r/w dscr 0 bit 0 r/w fiforst 0 fiforst the fiforst bit is used to reset the four cell transmit fifo. when fiforst is set to logic zero, the fifo operates normally. when fiforst is set to logic one, the fifo is immediately emptied and ignores writes. the fifo remains empty and continues to ignore writes until a logic zero is written to fiforst. null/unassigned cells are transmitted until a subsequent cell is written to the fifo. see section 13.9on resetting the receive and transmit fifos. dscr the dscr bit controls the scrambling of the cell payload. when dscr is a logic one, cell payload scrambling is disabled. when dscr is a logic zero, payload scrambling is enabled. in the case where hscr is logic one, the payload will be scrambled (along with the header) regardless of the setting of the dscr bit. hcsadd the hcsadd bit controls the addition of the coset polynomial, x 6 +x 4 +x 2 +1, to the hcs octet prior to insertion in the synchronous payload envelope. when hcsadd is a logic one, the polynomial is added, and the resulting hcs is inserted. when hcsadd is a logic zero, the polynomial is not added, and the unmodified hcs is inserted. hcsadd takes effect unconditionally regardless of whether a null/unassigned cell is being transmitted or whether the hcs octet has been read from the fifo.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 212 document id: pmc-1990267, issue 3 hcsb the active low hcsb bit enables the internal generation and insertion of the hcs octet into the transmit cell stream. when hcsb is logic zero, the hcs is generated and inserted internally. when the hcsb and ds27_53 register bits are logic one, the hcs octet read from the transmit fifo is inserted transparently into the transmit cell stream, but the txcp-50 will still generate and insert the hcs octet for idle cells. if hcsb is logic one and the 26-byte word data structure is selected (ds27_53 is logic zero), then no hcs octet is inserted in the transmit data stream. hcsdqdb the hcsdqdb bit controls the cell header octets included in the hcs calculation. when a logic one is written to hcsdqdb, header octets two, three, and four are included in the hcs calculation as required by ieee-802.6 dqdb specification. when a logic zero is written to hcsdqdb, all four header octets are included in the hcs calculation as required by the atm forum uni specification and itu-t recommendation i.432. hscr the header scramble enable bit, hscr, enables scrambling of the atm five octet header along with the payload. when set to logic one, the atm header and payload are both scrambled. when set to logic zero, the header is left unscrambled and payload scrambling is determined by the dscr bit. tcalevel0 the active high tca (and dtca[x]) level 0 bit, tcalevel0 determines what output tca (and dtca[x]) indicates when it de-asserts (transitions to logic zero if tcainv is logic zero, or transitions to logic one if tcainv is logic one). when tcalevel0 is set to logic one, tca (and dtca[x]) indicates that the transmit fifo is full and can accept no more writes. dtca[x] and tca, if polled, will de-assert on the rising tfclk edge when payload byte 47 (atm8=1) or payload word 23 (atm8=0) is sampled. when tcalevel0 is set to logic zero, tca (and dtca[x]) indicates that the transmit fifo is near full. dtca[x] and tca, if polled, will de-assert on the rising tfclk edge when payload byte 43 (atm8=1) or payload word 19 (atm8=0) is sampled. tptyp the tptyp bit selects even or odd parity for input tprty. when set to logic one, input tprty is the even parity bit for the tdat input bus. when set to logic zero, input tprty is the odd parity bit for the tdat input bus. when atm8 is set to logic one, the input bus consists of tdat[7:0]. when atm8 is logic zero, the input bus consists of tdat[15:0].
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 213 document id: pmc-1990267, issue 3 register 381h: txcp-50 configuration 2 bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r/w tcainv 0 bit 3 r/w fifodp[1] 0 bit 2 r/w fifodp[0] 0 bit 1 r/w dhcs 0 bit 0 r/w hcsctleb 0 hcsctleb the active low hcs control enable, hcsctleb bit enables the xoring of the hcs control byte with the generated hcs. when set to logic zero, the hcs control byte provided in the third word of the 27-byte word data structure is xored with the generated hcs. when set to logic one, xoring is disabled and the hcs control byte is ignored. dhcs the dhcs bit controls the insertion of hcs errors for diagnostic purposes. when dhcs is set to logic one, the hcs octet is inverted prior to insertion in the synchronous payload envelope. dhcs takes effect unconditionally regardless of whether a null/unassigned cell is being transmitted or whether the hcs octet has been read from the fifo. dhcs occurs after any error insertion caused by the control byte in the 27-byte word data structure. fifodp[1:0] the fifodp[1:0] bits determine the transmit fifo cell depth at which tca and dtca[x] de-assert. fifo depth control may be important in systems where the cell latency through the txcp-50 must be minimized. when the fifo is filled to the specified depth, the transmit cell available signal, tca (and dtca[x]) is de-asserted. note: regardless of what fill level fifodp[1:0] is set to, the transmit cell processor can store four complete cells. the selectable fifo cell depths are shown in table 23: table 23 txcp-50 fifo depth configurations fifodp[1] fifodp[0] fifo depth 0 0 4 cells 0 1 3 cells 1 0 2 cells 11 1 cell
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 214 document id: pmc-1990267, issue 3 tcainv the tcainv bit inverts the polarity of the tca (and dtca[x]) output signal. when tcainv is a logic one, the polarity of tca (and dtca[x]) is inverted (tca (and dtca[x]) at logic zero means there is transmit cell space available to be written to). when tcainv is a logic zero, the polarity of tca (and dtca[x]) is not inverted.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 215 document id: pmc-1990267, issue 3 register 382h: txcp-50 cell count status bit type function default bit 7 r/w xfere 0 bit 6 r xferi x bit 5 r ovr x bit 4 unused x bit 3 r/w reserved 1 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w reserved 0 reserved these bits should be set to their default values for proper operation xferi the xferi bit indicates that a transfer of transmit cell count data has occurred. a logic one in this bit position indicates that the transmit cell count registers have been updated. this update is initiated by writing to one of the transmit cell count register locations or to the s/uni-jet identification, master reset, and global monitor update register. xferi is set to logic zero when this register is read. ovr the ovr bit is the overrun status of the transmit cell count registers. a logic one in this bit position indicates that a previous transfer (indicated by xferi being logic one) has not been acknowledged before the next accumulation interval has occurred and that the contents of the transmit cell count registers have been overwritten. ovr is set to logic zero when this register is read. xfere the xfere bit enables the generation of an interrupt when an accumulation interval is completed and new values are stored in the transmit cell count registers. when xfere is set to logic one, the interrupt is enabled.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 216 document id: pmc-1990267, issue 3 register 383h: txcp-50 interrupt enable/status bit type function default bit 7 r/w tprtye 0 bit 6 r/w fovre 0 bit 5 r/w tsoce 0 bit 4 unused x bit 3 unused x bit 2 r tprtyi x bit 1 r fovri x bit 0 r tsoci x tsoci the tsoci bit is set high when the tsoc input is sampled high during any position other than the first word of the selected data structure. the write address counter is reset to the first word of the data structure when tsoc is sampled high. this bit is reset immediately after a read to this register. fovri the fovri bit is set high when an attempt is made to write into the fifo when it is already full. this bit is reset immediately after a read to this register tprtyi the tprtyi bit indicates if a parity error was detected on the tdat input bus. when logic one, the tprtyi bit indicates a parity error over the active tdat bus. the active tdat bus is tdat[15:0] when atm8 is tied low and is tdat[7:0] when atm8 is tied high. this bit is cleared when this register is read. odd or even parity is selected using the tptype bit. tsoce the tsoce bit enables the generation of an interrupt when the tsoc input is sampled high during any position other than the first word of the selected data structure. when tsoce is set to logic one, the interrupt is enabled. fovre the fovre bit enables the generation of an interrupt due to an attempt to write the fifo when it is already full. when fovre is set to logic one, the interrupt is enabled.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 217 document id: pmc-1990267, issue 3 tprtye the tprtye bit enables transmit parity interrupts. when set to logic one, parity errors are indicated on int and tprtyi. when set to logic zero, parity errors are indicated using bit tprtyi but are not indicated on output int.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 218 document id: pmc-1990267, issue 3 register 384h: txcp-50 idle cell header control bit type function default bit 7 r/w gfc[3] 0 bit 6 r/w gfc[2] 0 bit 5 r/w gfc[1] 0 bit 4 r/w gfc[0] 0 bit 3 r/w pti[2] 0 bit 2 r/w pti[1] 0 bit 1 r/w pti[0] 0 bit 0 r/w clp 1 clp the clp bit contains the eighth bit position of the fourth octet of the idle/unassigned cell pattern. cell rate decoupling is accomplished by transmitting idle cells when the txcp-50 detects that no outstanding cells exist in the transmit fifo. pti[3:0] the pti[3:0] bits contains the fifth, sixth, and seventh bit positions of the fourth octet of the idle/unassigned cell pattern. idle cells are transmitted when the txcp-50 detects that no outstanding cells exist in the transmit fifo. gfc[3:0] the gfc[3:0] bits contain the first, second, third, and fourth bit positions of the first octet of the idle/unassigned cell pattern. idle/unassigned cells are transmitted when the txcp-50 detects that no outstanding cells exist in the transmit fifo. the all-zeros pattern is transmitted in the vci and vpi fields of the idle cell.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 219 document id: pmc-1990267, issue 3 register 385h: txcp-50 idle cell payload control bit type function default bit 7 r/w payld[7] 0 bit 6 r/w payld[6] 1 bit 5 r/w payld[5] 1 bit 4 r/w payld[4] 0 bit 3 r/w payld[3] 1 bit 2 r/w payld[2] 0 bit 1 r/w payld[1] 1 bit 0 r/w payld[0] 0 payld[7:0] the payld[7:0] bits contain the pattern inserted in the idle cell payload. idle cells are inserted when the txcp-50 detects that the transmit fifo contains no outstanding cells. payld[7] is the most significant bit and is the first bit transmitted. payld[0] is the least significant bit.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 220 document id: pmc-1990267, issue 3 register 386h: txcp-50 transmit cell count (lsb) bit type function default bit 7 r tcell[7] x bit 6 r tcell[6] x bit 5 r tcell[5] x bit 4 r tcell[4] x bit 3 r tcell[3] x bit 2 r tcell[2] x bit 1 r tcell[1] x bit 0 r tcell[0] x register 387h: txcp-50 transmit cell count bit type function default bit 7 r tcell[15] x bit 6 r tcell[14] x bit 5 r tcell[13] x bit 4 r tcell[12] x bit 3 r tcell[11] x bit 2 r tcell[10] x bit 1 r tcell[9] x bit 0 r tcell[8] x
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 221 document id: pmc-1990267, issue 3 register 388h: txcp-50 transmit cell count (msb) bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r tcell[18] x bit 1 r tcell[17] x bit 0 r tcell[16] x tcell[18:0] the tcell[18:0] bits indicate the number of cells read from the transmit fifo and inserted into the transmission stream during the last accumulation interval. idle cells inserted into the transmission stream are not counted. a write to any one of the txcp-50 transmit cell counter registers or to the s/uni-jet identification, master reset, and global monitor update register (006h) loads the registers with the current counter value and resets the internal 19 bit counter to 1 or 0. the counter reset value is dependent on if there was a count event during the transfer of the count to the transmit cell counter registers. the counter should be polled every second to avoid saturating. the contents of these registers are valid after 24 ticlk periods containing cell header or payload data (line or plcp overhead periods do not count) after a transfer is triggered by a write to a txcp-50 transmit cell count register or the s/uni-jet identification, master reset, and global monitor update register (006h).
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 222 document id: pmc-1990267, issue 3 register 390h: ttb control bit type function default bit 7 r/w zeroen 0 bit 6 r/w rramacc 0 bit 5 r/w rtiuie 0 bit 4 r/w rtimie 0 bit 3 r/w per5 0 bit 2 r/w tnull 1 bit 1 r/w nosync 0 bit 0 r/w reserved 0 reserved the reserved bit should be set to logic zero for proper operation.nosync the nosync bit disables synchronization to the trail trace message. when nosync is set high, synchronization is disabled and the bytes of the trail trace message are captured by the ttb in a circular buffer. when nosync is set low, the ttb synchronizes to the byte with the most significant bit set high and places that byte in the first location in the capture buffer page. tnull the transmit null (tnull) bit controls the insertion of all-zeros into the outgoing trail trace message. the null insertion should be used when microprocessor accesses that change the outgoing trail trace message are being performed. when tnull is set high, an all-zeros byte is inserted to the transmit stream. when this bit is set low, the contents of the transmit trace buffer are sent. per5 the receive trace identifier persistency bit (per5) controls the number of times that persistency check is made in order to accept the received message. when this bit is set high, five identical message required in order to accept the message. when this bit set low, three unchanged consecutive messages are required. rtimie the receive trace identifier mismatch interrupt enable (rtimie) controls the activation of the interrupt output when comparison between the accepted trace identifier message and the expected trace identifier message changes state from match to mismatch and vice versa. when rtimie is set high, changes in match state will activate the interrupt output. when rtimie set low, trail trace message match state changes will not affect intb.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 223 document id: pmc-1990267, issue 3 rtiuie the receive trace identifier unstable interrupt enable (rtiuie) control the activation of the interrupt output when the receive trace identifier message changes state from stable to unstable and vice versa. when rtiuie is set high, changes in the state of the trail trace message unstable indication will activate the interrupt output. when rtiuie set low, trail trace unstable state changes will not effect intb. rramacc the receive ram access (rramacc) control bit is used by the microprocessor to identify that the access from the microprocessor is to the receive trace buffers (addresses 0 - 127) or to the transmit trace buffer (addresses 128 - 191). when rramacc is set high, subsequent microprocessor read and write accesses are directed to the receive side trace buffers. when rramacc is set low, microprocessor accesses are directed to the transmit side trace buffer. zeroen the zero enable bit (zeroen) enables tim assertion and removal based on an all-zeros path trace message string. when zeroen is set high, all-zeros path trace message strings are considered when entering and exiting tim states. when zeroen is set low, all-zeros path trace message strings are ignored.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 224 document id: pmc-1990267, issue 3 register 391h: ttb trail trace identifier status bit type function default bit 7 r busy x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r rtiui x bit 2 r rtiuv x bit 1 r rtimi x bit 0 r rtimv x rtimv the receive trace identifier mismatch value status bit (rtimv) is set high when the accepted message differs from the expected message. rtimv is set low when the accepted message is equal to the expected message. a mismatch is not declared if the accepted trail trace message string is all-zeros. rtimi the receive trace identifier mismatch indication status bit (rtimi) is set high when match/mismatch status of the trace identifier framer changes state. this bit (and the interrupt) is cleared when this register is read. rtiuv the receive trace identifier unstable value status bit (rtiuv) is set high when eight messages that differ from its immediate predecessor are received. rtiuv is set low and the unstable message count is reset when three or five (depending on per5 control bit) consecutive identical messages are received. rtiui the receive trace identifier unstable indication status bit (rtiuv) is set high when the stable/unstable status of the trace identifier framer changes state. this bit (and the interrupt) is cleared when this register is read. busy the busy bit reports whether a previously initiated indirect read or write to the trail trace ram has been completed. busy is set high upon writing to the ttb indirect address register, and stays high until the access has completed. at this point, busy is set low. this register should be polled to determine when either new data is available in the ttb indirect data register after an indirect read, or when the ttb is ready to accept another write access.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 225 document id: pmc-1990267, issue 3 register 392h: ttb indirect address bit type function default bit 7 r/w rwb 0 bit 6 r/w a[6] 0 bit 5 r/w a[5] 0 bit 4 r/w a[4] 0 bit 3 r/w a[3] 0 bit 2 r/w a[2] 0 bit 1 r/w a[1] 0 bit 0 r/w a[0] 0 a[6:0] the indirect read address bits (a[6:0]) indexes into the trail trace identifier buffers. when rramacc is set high, decimal addresses 0 to 63 reference the receive capture page while addresses 64 to 127 reference the receive expected page. the receive capture page contains the identifier bytes extracted from the receive g.832 e3 stream. the receive expected page contains the expected trace identifier message downloaded from the microprocessor. when rramacc is set low, decimal addresses 0 to 63 reference the transmit message buffer which contains the identifier message to be inserted in the tr bytes of the g.832 e3 transmit stream. in this case a[6] is a don't care (for example, address 0 and address 64 are indexes to the same location in the buffer). note: only the first 16 addresses need to be written with the trail trace message to be transmitted. rwb the access control bit (rwb) selects between an indirect read or write access to the static page of the trail trace message buffer. writing to this indirect address register initiates an external microprocessor access to the static page of the trail trace message buffer. when rwb is set high, a read access is initiated. the data read is available upon completion of the access in the ttb indirect data register. when rwb is set low, a write access is initiated. the data in the ttb indirect data register will be written to the addressed location in the static page.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 226 document id: pmc-1990267, issue 3 register 393h: ttb indirect data bit type function default bit 7 r/w d[7] x bit 6 r/w d[6] x bit 5 r/w d[5] x bit 4 r/w d[4] x bit 3 r/w d[3] x bit 2 r/w d[2] x bit 1 r/w d[1] x bit 0 r/w d[0] x d[7:0] the indirect data bits (d[7:0]) contain either the data read from a message buffer after an indirect read operation has completed, or the data to be written to the ram for an indirect write operation. note: the write data must be set up in this register before an indirect write is initiated. data read from this register reflects the value written until the completion of a subsequent indirect read operation.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 227 document id: pmc-1990267, issue 3 register 394h: ttb expected payload type label bit type function default bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w expld[2] 0 bit 1 r/w expld[1] 0 bit 0 r/w expld[0] 0 expld[2:0] the expld[2:0] bits contain the expected payload type label bits of the g.832 e3 maintenance and adaptation (ma) byte. the expld[2:0] bits are compared with the received payload type label extracted from the receive stream. a payload type label mismatch (pldm) is declared if the received payload type bits differs from the expected payload type. if enabled, an interrupt is asserted upon declaration and removal of pldm. for compatibility with old equipment that inserts 000b for unequipped or 001b for equipped, regardless of the payload type, the receive payload type label mismatch mechanism is based on table 24: table 24 ttb payload type match configurations expected received action 000 000 match 000 001 mismatch 000 xxx mismatch 001 000 mismatch 001 001 match 001 xxx match xxx 000 mismatch xxx 001 match xxx xxx match xxx yyy mismatch note 1. xxx, yyy = anything except 000b or 001b, and xxx is not equal to yyy. reserved the reserved bits must be written to logic zero for proper operation.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 228 document id: pmc-1990267, issue 3 register 395h: ttb payload type label control/status bit type function default bit 7 r/w rplduie 0 bit 6 r/w rpldmie 0 bit 5 r unused x bit 4 r unused x bit 3 r rpldui x bit 2 r rplduv x bit 1 r rpldmi x bit 0 r rpldmv x rpldmv the receive payload type label mismatch status bit (rpldmv) reports the match/mismatch status between the expected and the received payload type label. rpldmv is set high when the received payload type bits differ from the expected payload type written to the ttb expected payload type label register. the pldmv bit is set low when the received payload type matches the expected payload type. rpldmi the receive payload type label mismatch interrupt status bit (rpldmi) is set high when the match/mismatch status between the received and the expected payload type label changes state. this bit (and the interrupt) is cleared when this register is read. rplduv the receive payload type label unstable status bit (rplduv) reports the stable/unstable status of the payload type label bits in the receive stream. rplduv is set high when five labels that differ from its immediate predecessor are received. rplduv is set low and the unstable label count is reset when five consecutive identical labels are received. rpldui the receive payload type label unstable interrupt status bit (rpldui) is set high when the stable/unstable status of the path signal label changes state. this bit (and the interrupt) is cleared when this register is read.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 229 document id: pmc-1990267, issue 3 rpldmie the receive payload type label mismatch interrupt enable bit (rpldmie) controls the activation of the interrupt output when the comparison between received and the expected payload type label changes state from match to mismatch and vice versa. when rpldmie is set high, changes in match state activates the interrupt output. when rpldmie is set low, changes from match to mismatch or mismatch to match will not generate an interrupt. rplduie the receive payload type label unstable interrupt enable bit (rplduie) controls the activation of the interrupt output when the received payload type label changes state from stable to unstable and vice versa. when rplduie is set high, changes in stable state activates the interrupt output. when rplduie is set low, changes in the stable state will not generate and interrupt.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 230 document id: pmc-1990267, issue 3 register 398h: rboc configuration/interrupt enable bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w idle 0 bit 1 r/w avc 0 bit 0 r/w feace 0 feace the feace bit enables the generation of an interrupt when a valid feac(feac) code is detected. when a logic one is written to feace, the interrupt generation is enabled. av c the avc bit position selects the validation criterion used in determining a valid feac code. when a logic zero is written to avc, a feac code is validated when eight out of the last 10 received codes are identical. the feac code is removed when 2 out of the last 10 received code do not match the validated code. when a logic one is written to avc, a feac code is validated when four out of the last five received codes are identical. the feac code is removed when a single received feacs does not match the validated code. idle the idle bit enables the generation of an interrupt when a validated feac is removed. when a logic one is written to idle, the interrupt generation is enabled.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 231 document id: pmc-1990267, issue 3 register 399h: rboc interrupt status bit type function default bit 7 r idli x bit 6 r feaci x bit 5 r feac[5] x bit 4 r feac[4] x bit 3 r feac[3] x bit 2 r feac[2] x bit 1 r feac[1] x bit 0 r feac[0] x feac[5:0] the feac[5:0] bits contain the received feac channel codes. the feac[5:0] bits are set to all-ones ("111111") when no code has been validated. feaci the feaci bit is set to logic one when a new feac code is validated. the feac code value is contained in the feac[5:0] bits. the feaci bit position is set to logic zero when this register is read. idli the idli bit is set to logic one when a validated feac code is removed. the feac[5:0] bits are set to all-ones when the code is removed. the idli bit position is set to logic zero when this register is read.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 232 document id: pmc-1990267, issue 3 register 39ah: xboc code bit type function default bit 7 unused x bit 6 unused x bit 5 r/w feac[5] 1 bit 4 r/w feac[4] 1 bit 3 r/w feac[3] 1 bit 2 r/w feac[2] 1 bit 1 r/w feac[1] 1 bit 0 r/w feac[0] 1 feac[5:0] feac[5:0] contain the six bit code that is transmitted on the feac channel (feac). the transmitted code consists of a sixteen bit sequence that is repeated continuously. the sequence consists of eight ones followed by a zero, followed by the six bit code sequence transmitted in order feac0, feac1, .., feac5, followed by a zero. the all-ones sequence is inserted in the feac channel when feac[5:0] is written with all ones. note: if configured for j2 transmission format (tfrm[1:0] is 10 binary) and any of lcden, aisen, oofen, losen are set to logic one in the s/uni-jet data link and ferf/rai control, feac[5:0] in this register must all be set to logic one for proper rai transmission upon detection of lcd, phyais, lof, or los by the j2 frmr. otherwise, the boc code configured by the feac[5:0] bits of this register will be transmitted instead of the rai.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 233 document id: pmc-1990267, issue 3 register 39bh: s/uni-jet miscellaneous bit type function default bit 7 r/w aisoof 0 bit 6 r/w reserved 0 bit 5 r/w tprbs 0 bit 4 r/w reserved 0 bit 3 r/w tcell 0 bit 2 r/w loc_reset 0 bit 1 r/w forcelos 0 bit 0 r/w linesysclk 0 linesysclk linesysclk is used to select the high-speed system clock which the tdpr and rdlc transmit and receive hdlc controllers use as a reference. if linesysclk is set to logic one, then the rdlc uses the receive line clock (rclk[x]) and the tdpr uses the transmit line clock (ticlk[x]) as its high-speed system reference clock respectively. if linesysclk is set to logic zero, the rdlc uses the receive atm utopia interface clock (rfclk) and the tdpr uses the transmit atm utopia interface clock (tfclk) as its high- speed system reference clock respectively. the read/write access rate to the rdlc and tdpr are limited by their high-speed reference clock frequency. data and configuration settings can be written into the tdpr at a maximum rate equal to 1/8 of its high-speed reference clock frequency. data and status indications can be read from the tdpr at a maximum rate equal to 1/8 of its high-speed reference clock frequency. data and status indications can be read from the rdlc at a maximum rate equal to 1/10 of its high-speed reference clock frequency. instantaneous variations in the high-speed reference clock frequencies (e.g. jitter in the receive line clock) must be considered when determining the procedure used to read and write the tdpr and rdlc registers. forcelos forcelos is used to force a los condition on the transmit unipolar or bipolar data outputs tpos/tdato[x] and tneg[x]. when forcelos is logic one, the tpos/tdato[x] and tneg[x] outputs will be forced to logic zero. when forcelos is logic zero, the tpos/tdato[x] and tneg[x] outputs will operate normally. loc_reset loc_reset performs a software local reset of the corresponding quadrant of the s/uni- jet . when loc_reset is logic one, the corresponding quadrant of the s/uni-jet is held in a reset state. when loc_reset is logic zero, the quadrant is in normal operational mode.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 234 document id: pmc-1990267, issue 3 the loc_reset bit for quadrant 1 (register 09bh) also resets the chip level utopia bus. while the loc_reset for quadrant 1 is set to logic one, the s/uni-jet?s utopia bus will be held in a reset state, and will not function. in applications where the utopia bus is required, the loc_reset for quadrant 1 should not be permanently set to logic one. tcell when the tcell bit is a logic one, the tpohfp/tfpo/tmfpo/tgapclk/tcell pin takes on the tcell function, and pulses once for every transmitted cell (idle or unassigned). reserved the reserved bit should be set to logic zero for proper operation. tprbs register bit tprbs is used to insert a pseudo-random binary sequence into the transmit stream in place of other payload data. the exact nature of the prbs is configurable through the prgd registers (xa0h to xafh). reserved the reserved bit should be set to logic zero for proper operation. aisoof the aisoof bit allows the receive data output stream on rdato to be forced to all 1?s when the ds3, e3, or j2 frmr loses frame. when aisoof is set to logic one, rdato[x] will be forced to all 1?s when frame alignment is lost. when aisoof is set to logic zero, rdato will continue to output raw data even when frame alignment is lost. note: aisoof is only valid in framer-only mode (frmronly=1, s/uni-jet configuration 1 register).
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 235 document id: pmc-1990267, issue 3 register 39ch: s/uni-jet frmr lof status. bit type function default bit 7 r frmlof x bit 6 r/w frmlofe 0 bit 5 r frmlofi x bit 4 r/w j2sigthru 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w reserved 0 frmlofi the frmlofi bit shows that a transition has occurred on the frmlof state. when frmlofi is logic one, the frmlof state has changed since the last read of this register. the frmlofi bit is cleared whenever this register is read. frmlofe the frmlofe bit enables the generation of an interrupt due to a change in the frmlof state. when frmlofe is a logic one, the interrupt is enabled. frmlof the frmlof bit shows the current state of the e3/t3 lof or the j2 extended lof indication (depending on which mode is enabled). when frmlof is logic one, the framer has lost frame synchronization for greater than 1ms, 2ms, or 3ms depending on the setting of the lofint[1:0] bits in the s/uni-jet receive configuration register. j2sigthru the j2sigthru bit allows the signaling bits in timeslot 97 and 98 on the tdati stream to pass transparently through the j2 tran. when j2sigthru is logic one, timeslots 97 and 98 are passed transparently through from tdati. when j2sigthru is logic zero, timeslots 97 and 98 are sourced from the j2 tran ts97 signaling and j2 tran ts98 signaling registers. if j2sigthru is set to logic one and tprbs (s/uni-jet miscellaneous register) is also set to logic one, the transmitted prbs will continue through timeslots 97 and 98. j2sigthru is only valid in framer-only mode (frmronly=1, s/uni-jet configuration 1 register).
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 236 document id: pmc-1990267, issue 3 reserved the reserved bit must be programmed to logic zero for correct operation.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 237 document id: pmc-1990267, issue 3 register 3a0h: prgd control bit type function default bit 7 r/w pdr[1] 0 bit 6 r/w pdr[0] 0 bit 5 r/w qrss 0 bit 4 r/w ps 0 bit 3 r/w tinv 0 bit 2 r/w rinv 0 bit 1 r/w autosync 1 bit 0 r/w mansync 0 pdr[1:0] the pdr[1:0] bits select the content of the four pattern detector registers (at addresses xach to xafh) to be any one of the pattern receive registers, the error count holding registers, or the bit count holding registers. the selection is shown in table 25: table 25 prgd pattern detector register configuration pdr[1:0] pdr#1 pdr#2 pdr#3 pdr#4 00, 01 pattern receive (lsb) pattern receive pattern receive pattern receive (msb) 10 error count (lsb) error count error count error count (msb) 11 bit count (lsb) bit count bit count bit count(msb) qrss the qrss bit enables the zero suppression feature required when generating the qrss sequence. when qrss is a logic one, a one is forced in the tdato stream when the following 14 bit positions are all zeros. when qrss is a logic zero, the zero suppression feature is disabled. ps the ps bit selects the generated pattern. when ps is a logic one, a repetitive pattern is generated. when ps is a logic zero, a pseudo-random pattern is generated. the ps bit must be programmed to the desired setting before programming any other prgd registers, or the transmitted pattern may be corrupted. any time the setting of the ps bit is changed, the rest of the prgd registers should be reprogrammed. tinv the tinv bit controls the logical inversion of the generated data stream. when tinv is a logic one, the data is inverted. when tinv is a logic zero, the data is not inverted
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 238 document id: pmc-1990267, issue 3 rinv the rinv bit controls the logical inversion of the receive data stream before processing. when rinv is a logic one, the received data is inverted before being processed by the pattern detector. when rinv is a logic zero, the received data is not inverted autosync the autosync bit enables the automatic resynchronization of the pattern detector. the automatic resynchronization is activated when six or more bit errors are detected in the last 64 bit periods. when autosync is a logic one, the auto resync feature is enabled. when auto sync is a logic zero, the auto sync feature is disabled, and pattern resynchronization is accomplished using the mansync bit. mansync the mansync bit is used to initiate a manual resynchronization of the pattern detector. a low-to-high transition on mansync initiates the resynchronization.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 239 document id: pmc-1990267, issue 3 register 3a1h: prgd interrupt enable/status bit type function default bit 7 r/w synce 0 bit 6 r/w bee 0 bit 5 r/w xfere 0 bit 4 r syncv x bit 3 r synci x bit 2 r bei x bit 1 r xferi x bit 0 r ovr x synce the synce bit enables the generation of an interrupt when the pattern detector changes synchronization state. when synce is set to logic one, the interrupt is enabled. bee the bee bit enables the generation of an interrupt when a bit error is detected in the receive data. when bee is set to logic one, the interrupt is enabled. xfere the xfere bit enables the generation of an interrupt when an accumulation interval is completed and new values are stored in the receive pattern registers, the bit counter holding registers, and the error counter holding registers. when xfere is set to logic one, the interrupt is enabled. syncv the syncv bit indicates the synchronization state of the pattern detector. when syncv is a logic one the pattern detector is synchronized (the pattern detector has observed at least 32 consecutive error-free bit periods). when syncv is a logic zero, the pattern detector is out- of-sync (the pattern detector has detected six or more bit errors in a 64 bit period window). synci the synci bit indicates that the detector has changed synchronization state since the last time this register was read. if synci is logic one, then the pattern detector has gained or lost synchronization at least once. synci is set to logic zero when this register is read.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 240 document id: pmc-1990267, issue 3 bei the bei bit indicates that one or more bit errors have been detected since the last time this register was read. when bei is set to logic one, at least one bit error has been detected. bei is set to logic zero when this register is read. xferi the xferi bit indicates that a transfer of pattern detector data has occurred. a logic one in this bit position indicates that the pattern receive registers, the bit counter holding registers and the error counter holding registers have been updated. this update is initiated by writing to one of the pattern detector register locations, or by writing to the s/uni-jet identification, master reset, and global monitor update register (006h). xferi is set to logic zero when this register is read. ovr the ovr bit is the overrun status of the pattern detector registers. a logic one in this bit position indicates that a previous transfer (indicated by xferi being logic one) has not been acknowledged before the next accumulation interval has occurred and that the contents of the pattern receive registers, the bit counter holding registers and the error counter holding registers have been overwritten. ovr is set to logic zero when this register is read.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 241 document id: pmc-1990267, issue 3 register 3a2h: prgd length bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r/w pl[4] 0 bit 3 r/w pl[3] 0 bit 2 r/w pl[2] 0 bit 1 r/w pl[1] 0 bit 0 r/w pl[0] 0 pl[4:0] pl[4:0] determine the length of the generated pseudo random or repetitive pattern. the pattern length is equal to the value of pl[4:0] + 1.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 242 document id: pmc-1990267, issue 3 register 3a3h: prgd tap bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r/w pt[4] 0 bit 3 r/w pt[3] 0 bit 2 r/w pt[2] 0 bit 1 r/w pt[1] 0 bit 0 r/w pt[0] 0 pt[4:0] pt[4:0] determine the feedback tap position of the generated pseudo random pattern. the feedback tap position is equal to the value of pt[4:0] + 1.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 243 document id: pmc-1990267, issue 3 register 3a4h: prgd error insertion register bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w event 0 bit 2 r/w eir[2] 0 bit 1 r/w eir[1] 0 bit 0 r/w eir[0] 0 event a low-to-high transition on the event bit causes a single bit error to be inserted in the generated pattern. this bit must be cleared and set again for a subsequent error to be inserted. eir[2:0] the eir[2:0] bits control the insertion of a programmable bit error rate as indicated in table 26: table 26 prgd generated bit error rate configurations eir[2:0] generated bit error rate 000 no errors inserted 001 10 -1 010 10 -2 011 10 -3 100 10 -4 101 10 -5 110 10 -6 111 10 -7
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 244 document id: pmc-1990267, issue 3 register 3a8h: pattern insertion #1 bit type function default bit 7 r/w pi[7] 0 bit 6 r/w pi[6] 0 bit 5 r/w pi[5] 0 bit 4 r/w pi[4] 0 bit 3 r/w pi[3] 0 bit 2 r/w pi[2] 0 bit 1 r/w pi[1] 0 bit 0 r/w pi[0] 0 register 3a9h: pattern insertion #2 bit type function default bit 7 r/w pi[15] 0 bit 6 r/w pi[14] 0 bit 5 r/w pi[13] 0 bit 4 r/w pi[12] 0 bit 3 r/w pi[11] 0 bit 2 r/w pi[10] 0 bit 1 r/w pi[9] 0 bit 0 r/w pi[8] 0
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 245 document id: pmc-1990267, issue 3 register 3aah: pattern insertion #3 bit type function default bit 7 r/w pi[23] 0 bit 6 r/w pi[22] 0 bit 5 r/w pi[21] 0 bit 4 r/w pi[20] 0 bit 3 r/w pi[19] 0 bit 2 r/w pi[18] 0 bit 1 r/w pi[17] 0 bit 0 r/w pi[16] 0 register 3abh: pattern insertion #4 bit type function default bit 7 r/w pi[31] 0 bit 6 r/w pi[30] 0 bit 5 r/w pi[29] 0 bit 4 r/w pi[28] 0 bit 3 r/w pi[27] 0 bit 2 r/w pi[26] 0 bit 1 r/w pi[25] 0 bit 0 r/w pi[24] 0 pi[31:0] pi[31:0] contain the data that is loaded in the pattern generator each time a new pattern (pseudo random or repetitive) is to be generated. when a pseudo random pattern is to be generated, pi[31:0] should be set to 0xffffffff. the data is loaded each time pattern insertion register #4 is written. pattern insertion registers #1 - #3 should be loaded with the desired data before pattern register #4 is written.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 246 document id: pmc-1990267, issue 3 register 3ach: prgd pattern detector #1 bit type function default bit 7 r pd[7] 0 bit 6 r pd[6] 0 bit 5 r pd[5] 0 bit 4 r pd[4] 0 bit 3 r pd[3] 0 bit 2 r pd[2] 0 bit 1 r pd[1] 0 bit 0 r pd[0] 0 register 3adh: prgd pattern detector #2 bit type function default bit 7 r pd[15] 0 bit 6 r pd[14] 0 bit 5 r pd[13] 0 bit 4 r pd[12] 0 bit 3 r pd[11] 0 bit 2 r pd[10] 0 bit 1 r pd[9] 0 bit 0 r pd[8] 0
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 247 document id: pmc-1990267, issue 3 register 3aeh: prgd pattern detector #3 bit type function default bit 7 r pd[23] 0 bit 6 r pd[22] 0 bit 5 r pd[21] 0 bit 4 r pd[20] 0 bit 3 r pd[19] 0 bit 2 r pd[18] 0 bit 1 r pd[17] 0 bit 0 r pd[16] 0 register 3afh: prgd pattern detector #4 bit type function default bit 7 r pd[31] 0 bit 6 r pd[30] 0 bit 5 r pd[29] 0 bit 4 r pd[28] 0 bit 3 r pd[27] 0 bit 2 r pd[26] 0 bit 1 r pd[25] 0 bit 0 r pd[24] 0 pd[31:0] pd[31:0] contain the pattern detector data. the values contained in these registers are determined by the pdr[1:0] bits in the control register. when pdr[1:0] is set to 00 or 01, pd[31:0] contain the pattern receive register. the 32 bits received immediately before the last accumulation interval are present on pd[31:0}. pd[31] contains the first of the 32 received bits, pd[0] contains the last of the 32 received bits. when pdr[1:0] is set to 10, pd[31:0] contain the error counter holding register. the value in this register represents the number of bit errors that have been accumulated since the last accumulation interval. note: bit errors are not accumulated while the pattern detector is out- of-sync. when pdr[1:0] is set to 11, pd[31:0] contain the bit counter holding register. the value in this register represents the total number of bits that have been received since the last accumulation interval. the values of pd[31:0] are updated whenever one of the four prgd pattern detector registers is written or when register 006h, the s/uni-jet identification, master reset, and global monitor update register is written.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 248 document id: pmc-1990267, issue 3 register 40ch: s/uni-jet identification register bit type function default bit 7 r unused x bit 6 r device_id 1 bit 5 r unused x bit 4 r unused x bit 3 r unused x bit 2 r unused x bit 1 r unused x bit 0 r unused x this register provides a device identification to distinguish the s/uni-jet from a s/uni-qjet in applications where the s/uni-qjet is used for prototype purposes. device_id the device_id bit allows software to identify the device as a s/uni-jet. a logic one identifies the device as a s/uni-jet, whereas a logic zero identifies the device as a s/uni- qjet. to access this register, the iotst bit in the s/uni-jet master test register must first be set to logic one. the device_id bit can now be read. a logic zero must then be written back to the iotst bit to put the device back into normal mode of operation.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 249 document id: pmc-1990267, issue 3 12 test features description the test mode registers, shown in table 27, are used for production and board testing. during production testing, the test mode registers are used to apply test vectors. in this case, the test mode registers (as opposed to the normal mode registers) are selected when a[10] is high. during board testing, the digital output pins and the data bus are held in a high-impedance state by simultaneously asserting (low) the csb, rdb, and wrb inputs. all of the tsbs for the s/uni-jet are placed in test mode 0 so that device inputs may be read and device outputs may be forced through the microprocessor interface. refer to the section "test mode 0" for details. note: the s/uni-jet supports a standard ieee 1149.1 five-signal jtag boundary scan test port that can be used for board testing. all digital device inputs may be read and all digital device outputs may be forced through this jtag test port. table 27 test mode register memory map address register 000h-3ffh normal mode registers 400h master test register 708h splr test register 0 709h splr test register 1 70ah splr test register 2 70bh reserved 70ch splt test register 0 70dh splt test register 1 70eh splt test register 2 70fh splt test register 3 710h pmon test register 0 711h pmon test register 1 712h-71fh reserved 720h cppm test register 0 721h cppm test register 1 722h cppm test register 2 723h-72fh reserved 730h ds3 frmr test register 0 731h ds3 frmr test register 1 732h ds3 frmr test register 2 733h ds3 frmr test register 3 734h ds3 tran test register 0 735h ds3 tran test register 1 736h ds3 tran test register 2
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 250 document id: pmc-1990267, issue 3 address register 737h reserved 738h e3 frmr test register 0 739h e3 frmr test register 1 73ah e3 frmr test register 2 73bh-73fh reserved 740h e3 tran test register 0 741h e3 tran test register 1 742h e3 tran test register 2 743h reserved 744h j2 frmr test register 0 745h j2 frmr test register 1 746h j2 frmr test register 2 747h j2 frmr test register 3 748h-74bh reserved 74ch j2 tran test register 0 74dh j2 tran test register 1 74eh j2 tran test register 2 74fh j2 tran test register 3 750h rdlc test register 0 751h rdlc test register 1 752h rdlc test register 2 753h rdlc test register 3 754h rdlc test register 4 755h-757h reserved 758h tdpr test register 0 759h tdpr test register 1 75ah tdpr test register 2 75bh tdpr test register 3 75ch-75fh reserved 760h rxcp-50 test register 0 761h rxcp-50 test register 1 762h rxcp-50 test register 2 763h rxcp-50 test register 3 764h rxcp-50 test register 4 765h rxcp-50 test register 5 766h-77fh reserved 780h txcp-50 test register 0 781h txcp-50 test register 1 782h txcp-50 test register 2
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 251 document id: pmc-1990267, issue 3 address register 783h txcp-50 test register 3 784h txcp-50 test register 4 785h txcp-50 test register 5 786h-78fh reserved 790h ttb test register 0 791h ttb test register 1 792h ttb test register 2 793h-797h reserved 798h rboc test register 0 799h rboc test register 1 79ah xboc test register 1 79bh xboc test register 0 79ch-79fh reserved 7a0h prgd test register 0 7a1h prgd test register 1 7a2h prgd test register 2 7a3h prgd test register 3 7a4h-7ffh reserved notes 1. although writing values into unused register bits has no effect, it is recommended, to ensure software compatibility with future, feature-enhanced versions of the device, to write unused register bits with logic zero. reading back unused bits can produce either a logic one or a logic zero; therefore, unused register bits should be masked off by software when read. 2. writable test mode register bits are not initialized upon reset unless otherwise noted. 12.1 test mode 0 details in test mode 0, the s/uni-jet allows the logic levels on the device inputs to be read through the microprocessor interface and allows the device outputs to be forced to either logic level through the microprocessor interface. the iotst bit in the s/uni-jet master test register must be set to logic one to access the device i/o. to enable test mode 0, the iotst bit in the s/uni-jet master test register is set to logic one and the device should be left in its default state after reset unless otherwise noted. all test register 1 locations of all blocks must be written with the value 0. refer to table 27. reading the address locations shown in table 28 returns the values on the indicated inputs: table 28 test mode 0 input read address locations addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 40ch device_id 430h
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 252 document id: pmc-1990267, issue 3 addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 436h 444h 465h renb 3 466h radr[2] 4 radr[1] 4 radr[0] 4 rfclk 480h atm8 482h phy_adr[2] tadr[2] 1 tsoc tenb 2 tprty tfclk 483h phy_adr[1] phy_adr[0] tadr[1] 1 tadr[0] 1 484h tdat[15] tdat[14] tdat[13] tdat[12] tdat[11] tdat[10] tdat[9] tdat[8] 485h tdat[7] tdat[6] tdat[5] tdat[4] tdat[3] tdat[2] tdat[1] tdat[0] 50ch 50fh ref8ki 530h 536h 544h 565h 60ch 630h 636h 644h 665h radr[0] 4 70ch tiohm ticlk tpoh tpohins 730h rclk 736h toh tohins 744h rpos rneg 765h radr[1] 4 notes 1. before reading these values, the input must be set to the test state, tenb must be set to logic one, and tfclk must transition from logic zero to logic one. 2. before its value will be captured in the test register, tenb must be set to its test state and tfclk must transition from logic zero to logic one. 3. before its value will be captured in the test register renb must be set to its test state and rfclk must transition from logic zero to logic one. 4. before reading these values, the input must be set to the test state, renb must be set to logic one, and rfclk must transition from logic zero to logic one. writing the address locations shown in table 29 forces the outputs to the value in the corresponding bit position. note: zeros should be written to all unused test register locations.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 253 document id: pmc-1990267, issue 3 table 29 test mode 0 output write address locations addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 408h 40ah intb 1 40ch 410h intb 1 430h intb 1 434h 436h 432h 433h 44ch 44eh 450h intb 1 458h intb 1 463h rdat[15] 2 rdat[14] 2 rdat[13] 2 rdat[12] 2 rdat[11] 2 rdat[10] 2 rdat[9] 2 rdat[8] 2 464h rdat[7] 2 rdat[6] 2 rdat[5] 2 rdat[4] 2 rdat[3] 2 rdat[2] 2 rdat[1] 2 rdat[0] 2 465h rsoc 2 rprty 2 rca 3 intb 1 480h intb 1 490h intb 1 498h intb 1 4a2h intb 1 508h 50ah intb 1 50ch 510h intb 1 530h intb 1 534h 536h 532h 533h 54ch 54eh 550h intb 1 558h intb 1 565h rsoc 2 rprty 2 intb 1 580h intb 1 590h intb 1 598h intb 1
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 254 document id: pmc-1990267, issue 3 addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 5a2h intb 1 608h 60ah intb 1 60ch 610h intb 1 630h intb 1 634h 636h 632h 633h 64ch 64eh 650h intb 1 658h intb 1 665h rsoc 2 rprty 2 intb 1 680h intb 1 690h intb 1 698h intb 1 6a2h intb 1 708h rpohcl k rpoh ref8ko 70ah frmstat intb 1 70ch tpohfp tpohcl k 710h intb 1 730h intb 1 734h tclk 736h tohfp tohclk 732h roh rohcl] 733h rohfp 74ch tpos 74eh tneg 750h intb 1 758h intb 1 765h lcd rsoc 2 rprty 2 drca intb 1 780h dtca intb 1 790h intb 1 798h intb 1 7a2h intb 1
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 255 document id: pmc-1990267, issue 3 notes 1. all these register bits must be set to logic zero for the intb output to be tri-stated. if any one of these register bits is a logic one, then intb will be driven to logic zero. 2. to enable these outputs, after setting the desired state, radr[0] must be set to logic zero, renb must be set to logic one, bit 4 of register 09bh must be set to logic one, and rfclk must transition from logic zero to logic one. 3. to enable this output, after setting the desired state, radr[2:0] must be set equal to phy_adr[2:0], radr[1:0] must be set equal to binary 00, rfclk must transition from logic zero to logic one. 4. to enable this output, after setting the desired state, tadr[2:0] must be set equal to phy_adr[2:0], tadr[1:0] must be set equal to binary 00, tfclk must transition from logic zero to logic one. 5. bit 1 of this register must be logic zero. 12.2 jtag test port the s/uni-jet jtag test access port (tap) allows access to the tap controller and the 4 tap registers: instruction, bypass, device identification and boundary scan. tap enables the following: ? reading device input logic levels. ? forcing device output. ? identifying the device. ? bypassing the device scan path. for more details on the jtag port, please refer to the error! reference source not found. section. table 30 instruction register length - 3 bits instructions selected register instruction codes, ir[2:0] extest boundary scan 000 idcode identification 001 sample boundary scan 010 bypass bypass 011 bypass bypass 100 stctest boundary scan 101 bypass bypass 110 bypass bypass 111
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 256 document id: pmc-1990267, issue 3 table 31 identification register length 32 bits version number 2h part number 7346h manufacturer's identification code 0cdh device identification 273460cdh table 32 boundary scan register length - 198 bits pin/enable register bit cell type id bit pin/enable register bit cell type id bit tdat[15] 1 0 in_cell 0 tpohfp 87 out_cell (0) tdat[14] 1 in_cell 0 unconnected 88:90 out_cell (0) tdat[13] 2 in_cell 1 lcd 91 out_cell (0) tdat[12] 3 in_cell 0 unconnected 92:94 out_cell (0) tdat[11] 4 in_cell 0 rpoh 95 out_cell (0) tdat[10] 5 in_cell 1 unconnected 96:98 out_cell (0) tdat[9] 6 in_cell 1 rpohclk 99 out_cell (0) tdat[8] 7 in_cell 1 unconnected 100:102 out_cell (0) tdat[7] 8 in_cell 0 ref8ko 103 out_cell (0) tdat[6] 9 in_cell 0 unconnected 104:106 out_cell (0) tdat[5] 10 in_cell 1 frmstat 107 out_cell (0) tdat[4] 11 in_cell 1 unconnected 108:110 out_cell (0) tdat[3] 12 in_cell 0 ref8ki 111 in_cell (0) tdat[2] 13 in_cell 1 rohclk 112 out_cell (0) tdat[1] 14 in_cell 0 unconnected 113;115 out_cell (0) tdat[0] 15 in_cell 0 rohfp 116 out_cell (0) tfclk 16 in_cell 0 unconnected 117:119 out_cell (0) tied to ?1? 17 in_cell 1 roh 120 out_cell (0) tied to ?1? 18 in_cell 1 unconnected 121:123 out_cell (0) tadr[2] 19 in_cell 0 tohfp 124 out_cell (0) tadr[1] 20 in_cell 0 unconnected 125:127 out_cell (0) tadr[0] 21 in_cell 0 tohclk 128 out_cell (0) tprty 22 in_cell 0 unconnected 129:131 out_cell (0) tsoc 23 in_cell 0 tohins 132 in_cell (0) tenb 24 in_cell 1 tied to ?0? 133:135 in_cell (0) tca 25 out_cell 1 toh 136 in_cell (0) tca_oeb 2 26 out_cell 0 tied to ?0? 137:139 in_cell (0) dtca 27 out_cell 0 rclk 140 in_cell (0) unconnected 28 out_cell 1 tied to ?0? 141:143 in_cell (0)
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 257 document id: pmc-1990267, issue 3 pin/enable register bit cell type id bit pin/enable register bit cell type id bit unconnected 29 out_cell 1 rneg 144 in_cell (0) unconnected 30 out_cell 0 tied to ?0? 145;147 in_cell (0) phy_adr[2] 31 in_cell 1 rpos 148 in_cell (0) phy_adr[1] 32 in_cell (1) tied to ?0? 149:151 in_cell (0) phy_adr[0] 33 in_cell (1) tclk 152 out_cell (0) atm8 34 in_cell (0) unconnected 153:155 out_cell (0) drca 35 out_cell (0) tneg 156 out_cell (0) unconnected 36 out_cell (0) unconnected 157:159 out_cell (0) unconnected 37 out_cell (0) tpos 160 out_cell (0) unconnected 38 out_cell (0) unconnected 161:163 out_cell (0) rca 39 out_cell (0) intb 164 out_cell (0) rca_oeb 3 40 out_cell (0) rstb 165 in_cell (0) rsoc 41 out_cell (0) wrb 166 in_cell (0) renb 42 in_cell (0) rdb 167 in_cell (0) rfclk 43 in_cell (0) ale 168 in_cell (0) tied to ?1? 44 in_cell (0) csb 169 in_cell (0) tied to ?1? 45 in_cell (0) a[10:0] 170:180 in_cell (0) radr[2] 46 in_cell (0) d[7] 181 io_cell (0) radr[1] 47 in_cell (0) doenb [7] 5 182 out_cell (0) radr[0] 48 in_cell (0) d[6] 183 io_cell (0) rprty 49 out_cell (0) doenb[6] 5 184 out_cell (0) rdat[15:0] 50:65 out_cell (0) d[5] 185 io_cell (0) rx_oeb 4 66 out_cell (0) doenb [5] 5 186 out_cell (0) ticlk 67 in_cell (0) d[4] 187 io_cell (0) tied to ?0? 68:70 in_cell (0) doenb [4] 5 188 out_cell (0) tiohm 71 in_cell (0) d[3] 189 io_cell (0) tied to ?0? 72:73 in_cell (0) doenb [3] 5 190 out_cell (0) tied to ?1? 74 in_cell (0) d[2] 191 io_cell (0) tpoh 75 in_cell (0) doenb [2] 5 192 out_cell (0) tied to ?0? 76:78 in_cell (0) d[1] 193 io_cell (0) tpohins 79 in_cell (0) doenb [1] 5 194 out_cell (0) tied to ?0? 80:82 in_cell (0) d[0] 195 io_cell (0) tpohclk 83 out_cell (0) doenb [0] 5 196 out_cell (0) unconnected 84:86 out_cell (0) hiz 6 197 out_cell (0) notes 1. tdat[15] is the first bit of the boundary scan chain. 2. tca_oeb will set tca to tri-state when set to logic one. when set to logic zero, tca will be driven. 3. rca_oeb will set rca to tri-state when set to logic one. when set to logic zero, rca will be driven.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 258 document id: pmc-1990267, issue 3 4. rx_oeb will set rdat[15:0], rprty, and rsoc to tri-state when set to logic one. when set to logic zero, rdat[15:0], rprty, and rsoc will be driven. 5. the doenb signals will set the corresponding bidirectional signal (the one preceding the doenb in the boundary scan chain ? see note 1 also) to an output when set to logic zero. when set to logic one, the bidirectional signal will be tri-stated. 6. hiz will set all outputs not controlled by tca_oeb, rca_oeb, rx_oeb, and doenb to tri-state when set to logic one. when set to logic zero, those outputs will be driven.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 259 document id: pmc-1990267, issue 3 13 operation 13.1 software initialization sequence using the following software initialization sequence puts the s/uni-jet in a normal power consumption state. pmc-sierra? strongly recommends using this reset sequence to guarantee the device?s long term reliability. note: after a reset, the s/uni-jet may start using more power than is required. while the device?s normal operations are not altered, the excessive power consumption can cause the device to give off high levels of heat, which in turn, could lead to future problems with the device. to initialize the device: ? reset the s/uni-jet. ? set iotst (bit 2) in the master test register (datasheet pg. 291) to '1' (by writing 00000100 to register 400h). ? put the s/uni-jet receive cell processor (rxcp) into test mode by writing: 00000101 to test register 461h 00000101 to test register 561h 00000101 to test register 661h 00000101 to test register 761h ? set the s/uni-jet receive cell processor block built in set test (bist) controls signals by writing: 01000000 to test register 462h 01000000 to test register 562h 01000000 to test register 662h 01000000 to test register 762h 10101010 to test register 463h 10101010 to test register 563h 10101010 to test register 663h 10101010 to test register 763h ? put the s/uni-jet transmit cell processor (txcp) into test mode by writing: 00000011 to test register 481h 00000011 to test register 581h 00000011 to test register 681h 00000011 to test register 781h
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 260 document id: pmc-1990267, issue 3 ? set the s/uni-jet transmit cell processor block built in set test (bist) controls signals by writing: 10000000 to test register 480h 10000000 to test register 580h 10000000 to test register 680h 10000000 to test register 780h 10101010 to test register 482h 10101010 to test register 582h 10101010 to test register 682h 10101010 to test register 782h ? toggle ref8ki (pin t3, datasheet page 29) signal several times. this provides the clock to the ram. ref8ki is the test clock used by the txcp and rxcp blocks when in test mode. ? set iotst (bit 2) in the master test register (datasheet pg. 291) to '0' (by writing 00000000 to register 400h). ? resume normal device programming. 13.2 register settings for basic configurations table 33 register settings for basic configurations mode of operation s/uni-jet registers (values in hexadecimal) 300 302 303 304 308 30c 330 334 338 339 340 341 344 34c 360 361 380 39b t3 c-bit adm c00000f800008301-- -- -- -- -- -- 04040400 t3 m23 adm c00000f800008200-- -- -- -- -- -- 04040400 t3 c-bit plcp 40 00 00 f8 04 04 83 01 -- -- -- -- -- -- 04 00 04 00 t3 m23 plcp 40 00 00 f8 04 04 82 00 -- -- -- -- -- -- 04 00 04 00 t3 c-bit framer only 1 50 00 00 78 00 00 83 01 -- -- -- -- -- -- -- -- -- 01 t3 m23 framer only 1 50 00 00 78 00 00 82 00 -- -- -- -- -- -- -- -- -- 01 e3 g.832 adm c0 40 40 f8 00 00 -- -- 04 00 01 01 -- -- 04 08 04 00 e3 g.832 framer only 1 50 40 40 78 00 00 -- -- 04 00 01 01 -- -- -- -- -- 01 e3 g.751 adm c0 40 40 f8 00 44 -- -- 00 00 00 41 -- -- 04 08 04 00 e3 g.751 plcp 40 40 40 f8 44 44 -- -- 00 04 00 41 -- -- 04 00 04 00 e3 g.751 framer only 1 50 40 40 78 00 00 -- -- 00 00 00 01 -- -- -- -- -- 01 j2 adm c08080f80000-- -- -- -- -- 030e04080400 j2 framer only 1 50 80 80 78 00 00 -- -- -- -- -- 03 0e -- -- 01 e1 plcp 40 c0 c0 -- c4 c4 -- -- -- -- -- -- -- 04 00 04 00 e1 adm 40 c0c0-- c0c0-- -- -- -- -- -- -- 04 00 04 00
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 261 document id: pmc-1990267, issue 3 mode of operation s/uni-jet registers (values in hexadecimal) 300 302 303 304 308 30c 330 334 338 339 340 341 344 34c 360 361 380 39b t1 plcp 40 c0 c0 -- 84 84 -- -- -- -- -- -- -- 04 00 04 00 t1 adm 40c0c0--8080---------- ----04000400 external framer adm 2 40 c0 c0 -- 01 01 -- -- -- -- -- -- -- 04 00 4 04 00 notes 1. in framer only modes, tgapclk and rgapclk are enabled by programming register 301h to 30ch. 2. byte, nibble, or bit alignment of the atm cell bytes to the line overhead is configured using the tocta bit in register 300h, and the form[1:0] bits in register 30ch. 3. unipolar mode is selected for ds3, e3, and j2 modes by setting the tuni bit to logic one in register 302h and the uni bit in 330h, 338h, and 344h respectively. w hen the ds3, e3, or j2 framers are bypassed, unipolar mode is selected by default. 4. bit, nibble, and byte alignment of the atm cell octets to the arbitrary external frame overhead is set using the align[1:0] bits of register 361h. 5. atm cells are configured to have the coset polynomial added to the hcs byte and payload scrambling/descrambling is enabled. 6. atm idle cell header octets h1, h2, h3, and h4 are configured to be 00h 00h 00h 01h respectively. 13.3 plcp frame formats the s/uni-jet supports four different plcp frame formats: ? ds3 plcp. ? ds1. ? g.751 e3. ? e1. the structure of each of these formats is quite similar, and is illustrated in figure 8 through figure 11.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 262 document id: pmc-1990267, issue 3 figure 8 ds3 plcp frame format a1 a2 p11 z6 atm cell a1 a2 p10 z5 a1 a2 p9 z4 a1 a2 p8 z3 a1 a2 p7 z2 a1 a2 p6 z1 a1 a2 p5 f1 a1 a2 p4 b1 a1 a2 p3 g1 a1 a2 p2 m2 a1 a2 p1 m1 a1 a2 p0 c1 trailer atm cell atm cell atm cell atm cell atm cell atm cell atm cell atm cell atm cell atm cell atm cell plcp frame rate 125 s 53 octets poh 13 or 14 nibbles framing (3 octets) the ds3 plcp frame provides the transmission of 12 atm cells every 125 s. the plcp frame is nibble aligned to the overhead bits in the ds3 frame; however, there is no relationship between the start of the plcp frame and the start of the ds3 m-frame. a trailer is inserted at the end of each plcp frame. the number of nibbles inserted (13 or 14) is varied continuously such that the resulting plcp frame rate can be locked to an 8 khz reference. figure 9 ds1 plcp frame format a1 a2 p9 z4 a1 a2 p8 z3 a1 a2 p7 z2 a1 a2 p6 z1 a1 a2 p5 f1 a1 a2 p4 b1 a1 a2 p3 g1 a1 a2 p2 m2 a1 a2 p1 m1 a1 a2 p0 c1 trailer atm cell atm cell atm cell atm cell atm cell atm cell atm cell atm cell atm cell atm cell plcp frame rate 3 ms 53 octets poh framing (3 octets) 6 octets
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 263 document id: pmc-1990267, issue 3 the ds1 plcp frame provides the transmission of 10 atm cells every 3 ms. the plcp frame is octet aligned to the framing bit in the ds1 frame; there is no relationship between the start of the plcp frame, and the start of the ds1 frame. a trailer is inserted at the end of each plcp frame. the number of octets inserted is always six, and cannot be varied. figure 10 g.751 e3 plcp frame format a1 a2 p8 z3 a1 a2 p7 z2 a1 a2 p6 z1 a1 a2 p5 f1 a1 a2 p4 b1 a1 a2 p3 g1 a1 a2 p2 m2 a1 a2 p1 m1 a1 a2 p0 c1 trailer 17,18,19,20, or 21 octets atm cell atm cell atm cell atm cell atm cell atm cell atm cell atm cell atm cell plcp frame rate 125 s 53 octets poh framing (3 octets) the g.751 e3 plcp frame provides the transmission of 9 atm cells every 125 s. the plcp frame is octet aligned to the 16 overhead bits in the itu-t recommendation g.751 e3 frame; there is no relationship between the start of the plcp frame, and the start of the e3 frame. a trailer is inserted at the end of each plcp frame. the number of octets inserted is nominally 18, 19, or 20, and is based on the number of e3 overhead octets (4, 5, or 6) that have been inserted during the plcp frame period. the nominal octet stuffing can be varied by 1 octet to allow the e3 plcp frame to be locked to an external 8 khz reference. thus the trailer can be 17, 18, 19, 20, or 21 octets in length.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 264 document id: pmc-1990267, issue 3 figure 11 e1 plcp frame format a1 a2 p9 z4 a1 a2 p8 z3 a1 a2 p7 z2 a1 a2 p6 z1 a1 a2 p5 f1 a1 a2 p4 b1 a1 a2 p3 g1 a1 a2 p2 m2 a1 a2 p1 m1 a1 a2 p0 c1 atm cell atm cell atm cell atm cell atm cell atm cell atm cell atm cell atm cell atm cell plcp frame rate 2.375 ms 53 octets poh framing (3 octets) the e1 plcp frame provides the transmission of 10 atm cells every 2.375 ms. thirty of the thirty-two available e1 channels are used for transporting the plcp frame. the remaining two channels are reserved for e1 framing and signaling functions. the plcp frame is octet aligned to the channel boundaries in the e1 frame. the plcp frame is aligned to the 125 s e1 frame (the a1 octet of the first row of the plcp frame is inserted in timeslot 1 of the e1 frame). 13.3.1 plcp path overhead octet processing table 34 plcp overhead processing overhead field transmit operation receive operation a1, a2: frame alignment pattern inserts the plcp frame alignment pattern (f628h) searches the receive stream for the plcp frame alignment pattern. when the pattern has been detected for two consecutive rows, along with two valid, and sequential path overhead identifier octets, the s/uni-jet declares in- frame. note: the atm cell boundaries are implicitly known when the plcp frame is located, thus cell delineation is accomplished by locating the plcp frame. when errors are detected in both octets in a single row, or when errors are detected in two consecutive path overhead identifier octets, the s/uni-jet declares an oof defect. the lof defect is an integrated version of the oof defect state. po-p11: path overhead identifier inserts the path overhead identifier codes in accordance with the plcp frame alignment. see table 35. identifies the plcp path overhead bytes by monitoring the sequence of the poi bytes. z1-z6: these octets are unused and are these octets are ignored and are extracted on
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 265 document id: pmc-1990267, issue 3 overhead field transmit operation receive operation growth: nominally programmed with all zeros. access to these octets is provided by the plcp transmit overhead access port. the rpoh pin. f1: user channel this octet is unused and the value inserted in this octet is controlled by an internal register or by tpoh pin. this octet is ignored and is extracted on the rpoh pin. b1: bit interleaved parity this octet contains an 8-bit interleaved parity (bip) calculated across the entire plcp frame (excluding the a1, a, pn octets and the trailer). the b1 value is calculated based on even parity and the value inserted in the current frame is the bip result calculated for the previous frame. the bit interleaved parity is calculated for the current frame and stored. the b1 octet contained in the subsequent frame is extracted and compared against the calculated value. differences between the two values provide an indication of the end-to-end bit error rate. these differences are accumulated in a counter in the cppm block. g1: path status the first four bit positions provide a plcp febe function and indicates the number of b1 errors detected at the near end. the febe field has nine legal values (0000b-1000b) indicating between zero and eight b1 errors. the fifth bit position is used to transmit plcp yellow alarm. the last three bit positions provide the link status signal used in ieee- 802.6 dqdb implementations. yellow alarm and link status signal insertion is controlled by the internal registers or by tpoh pin. the g1 byte provides the plcp febe function and is accumulated in an a counter in the cppm block. plcp yellow alarm is detected or removed when the yellow bit is set to logic one or zero for ten consecutive frames. the yellow alarm state and the link status signal state are contained in the splr status register. m1, m2: control information these octets carry the dqdb layer management information. internal register controls the nominal value inserted in these octets. these octets are unused in atm forum t3 uni 3.0 specification. these octets are ignored and are extracted on the rpoh pin. c1: cycle/stuff counter the coding of this octet depends on the plcp frame format. for ds1 and e3 plcp formats, this octet is programmed with all zeros. for the ds3 plcp format, this octet indicates the number of stuff nibbles (13 or 14) at the end of each plcp frame. the c1 value is varied in a three frame cycle where the first frame always contains 13 stuff nibbles, the second frame always contains 14 nibbles, and the third frame contains 13 or 14 nibbles. the stuffing may be varied by a nibble so that the plcp frame rate can be locked to an external 8 khz interprets the trailer length according to the selected plcp frame format and the received c1 code.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 266 document id: pmc-1990267, issue 3 overhead field transmit operation receive operation timing reference from ref8ki, a looptimed 8 khz reference, or fixed stuffing via the fixstuff bit in the splt configuration register. see table 36. for the g.751 e3 plcp format, this octet indicates the number of stuff octets (17 to 21) at the end of the plcp frame. depending on the alignment of the g.751 e3 frame to the e3 plcp frame, 18, 19 or 20 octets are nominally stuffed. the stuffing may be varied by 1 octet so that the plcp frame rate can be locked to an external 8 khz timing reference from ref8ki. the s/uni-jet also supports fixed timing using the fixstuff bit in the splt configuration register. see table 37. table 35 plcp path overhead identifier codes poi poi code (hex) p11 2c p10 29 p9 25 p8 20 p7 1c p6 19 p5 15 p4 10 p3 0d p2 08 p1 04 p0 01 table 36 ds3 plcp trailer length c1(hex) frame/trailer length ff 1 (13 nibbles) 00 2 (14 nibbles) 66 3 (13 nibbles) 99 3 (14 nibbles)
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 267 document id: pmc-1990267, issue 3 table 37 e3 plcp trailer length c1(hex) trailer length 3b 17 octets 4f 18 octets 75 19 octets 9d 20 octets a7 21 octets 13.4 ds3 frame format the s/uni-jet supports both m23 and c-bit parity ds3 framing formats. this format can be extended to support direct byte mapping or plcp mapping of atm cells. an overview of the ds3 frame format is shown in figure 12. figure 12 ds3 frame structure x 1 payload f 1 payload c 1 payload f 2 payload c 2 payload f 3 payload c 3 payload f 4 payload x 2 payload f 1 payload c 1 payload f 2 payload c 2 payload f 3 payload c 3 payload f 4 payload p 1 payload f 1 payload c 1 payload f 2 payload c 2 payload f 3 payload c 3 payload f 4 payload p 2 payload f 1 payload c 1 payload f 2 payload c 2 payload f 3 payload c 3 payload f 4 payload m 1 payload f 1 payload c 1 payload f 2 payload c 2 payload f 3 payload c 3 payload f 4 payload m 2 payload f 1 payload c 1 payload f 2 payload c 2 payload f 3 payload c 3 payload f 4 payload m 3 payload f 1 payload c 1 payload f 2 payload c 2 payload f 3 payload c 3 payload f 4 payload 680 bits (8 blocks of 84+1 bits) 84 bits 1 m-subframe 2 3 4 5 6 7 the ds3 receiver decodes a b3zs-encoded signal and provides indications of lcvs. the b3zs decoding algorithm and the lcv definition are software selectable. while in-frame, the ds3 receiver continuously checks for lcv, m-bit or f-bit framing bit errors, and p-bit parity errors. when c-bit parity mode is selected, both c-bit parity errors and febes are accumulated. when the c-bit parity framing format is detected, both the feac channel and the pmdl are extracted. hdlc messages in the pmdl are received by an internal data link receiver. the ds3 transmitter allows for the insertion of the overhead bits into a ds3 bit stream and produces a b3zs-encoded signal. status signals such as ferf, ais, and idle signal can be inserted when the transmission of these signals is enabled
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 268 document id: pmc-1990267, issue 3 the processing of the overhead bits in the ds3 frame is described in table 38. in the transmit direction, the overhead bits can be inserted on a bit-by-bit basis from a user supplied data stream using the toh, tohins, tohfp, and tohclk signals. in the receive direction, most of the overhead bits our brought out serially on the roh data stream. table 38 ds3 frame overhead operation control bit transmit operation receive operation xx: x-bit channel inserts the ferf signal on the x-bits. monitors and detects changes in the state of the ferf signal on the x-bits. px: p-bit channel calculates the parity for the payload data over the previous m-frame and inserts it into the p1 and p2 bit positions. calculates the parity for the received payload. errors are accumulated in internal registers. mx: m-frame alignment signal generates the m-frame alignment signal (m1=0, m2=1, m3=0). finds the m-frame alignment by searching for the f-bits and the m-bits. oof is removed if the m-bits are correct for three consecutive m- frames while no discrepancies have occurred in the f-bits. fx: m-subframe alignment signal generates the m-subframe signal (f1=1, f2=0, f3=0, f4=1). finds m-frame alignment by searching for the f-bits and the m-bits. oof is removed if the m-bits are correct for three consecutive m- frames while no discrepancies have occurred in the f-bits. cx: c-bit channels m23 operation: the c bits are passed through transparently in m23 framer only mode except for the c-bit parity id bit which toggles every m- frame. in m23 atm applications, the c bits other than the parity id bit are forced to logic one. c-bit parity operation: the c-bit parity id bit is forced to logic one. the second c-bit in m- subframe 1 is set to logic one. the third c-bit in m-subframe 1 provides a far-end alarm and control (feac) signal. the feac channel is sourced by the xboc block. the 3 c-bits in m- subframe 3 carry path parity information. the value of these 3 c-bits is the same as that of the p-bits. the 3 c-bits in m- subframe 4 are the febe bits. the 3 c-bits in m-subframe 5 contain the 28.2 kbit/s path maintenance datalink. the remaining c-bits are unused and set to logic one. the state of the c-bit parity id bit is stored in a register. this bit indicates whether an m23 or c-bit parity format is received. c-bit parity operation: the feac channel on the third c-bit in m- subframe 1 is detected by the rboc block. path parity errors and febes on the c-bits in m-subframes 3 and 4 are accumulated in counters. the path maintenance datalink signal is extracted by the receive hdlc controller.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 269 document id: pmc-1990267, issue 3 13.5 g.751 e3 frame format the s/uni-jet provides support for the g.751 e3 frame format, shown in figure 13. this format can be extended to allow for direct byte mapping or plcp mapping of atm cells. figure 13 g.751 e3 frame structure 1 1 1 1 0 1 0 0 0 0 rai na c 11 c 21 c 31 c 41 c 12 c 22 c 32 c 42 c 13 c 23 c 33 c 43 j 1 j 2 j 3 j 4 372 payload bits 380 payload bits 380 payload bits 376 payload bits the processing of the overhead bits in the g.751 e3 frame is described in table 39. in the transmit direction, the overhead bits can be inserted on a bit-by-bit basis from a user supplied data stream using the toh, tohins, tohfp, and tohclk signals. in the receive direction, most of the overhead bits are brought out serially on the roh data stream. when used to transport atm cells in either atm direct mapping mode or with plcp framing, bits 13, 14, 15, and 16 of the e3 frame (directly following the rai and na bits) are set to 1, 1, 0 and 0. table 39 g.751 e3 frame overhead operation control bit transmit operation receive operation frame alignment signal inserts the frame alignment signal 1111010000b. finds frame alignment by searching for the frame alignment signal. when the pattern has been detected for three consecutive frames, an in-frame condition is declared. when errors are detected in four consecutive frames, an oof condition is declared. rai: rai optionally asserts the rai signal under a register control or when los, oof, ais and lcd conditions are detected. extracts the rai signal and outputs it on the roh output pin. the state of the rai signal is also written to a register bit. na: national use bit asserts the national use bit under a register control or from the internal hdlc controller. extracts the national use bit and stores the value in a register bit. cjk: justification service bits when the device is configured as an e3 g.751 framer device, the justification service bits can be inserted on the tdati input pin the same way as normal payload data. when the device is configured for atm application, the justification service bits are used as payload bits. extracts the justification service bits on the roh output pin when the cjk bits are configured as overhead.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 270 document id: pmc-1990267, issue 3 control bit transmit operation receive operation jk: tributary justification bits when the device is configured as a e3 g.751 framer, the tributary justification bits can be inserted on the tdati input pin the same way as normal payload data. when the device is configured for atm application, the tributary justification bits are used a payload bits. extracts the tributary justification bits on the roh output pin when the jk bits are configured as overhead. 13.6 g.832 e3 frame format the s/uni-jet provides support for the g.832 e3 frame format. this format can be extended to allow for direct byte mapping of atm cells. the g.832 e3 frame format is shown in figure 14. figure 14 g.832 e3 frame structure fa1 em tr ma nr gc 530 octet payload fa2 9 rows 59 columns the processing of the overhead bits in the g.832 e3 frame is described in table 40. in the transmit direction, the overhead bits can be inserted on a bit-by-bit basis from a user supplied data stream using the toh, tohins, tohfp, and tohclk signals. in the receive direction, the overhead bits are brought out serially on the roh data stream. table 40 g.832 e3 frame overhead operation control transmit operation receive operation fa1, fa2: frame alignment pattern inserts the g.832 e3 frame alignment pattern (f628h). searches the receive stream for the g.832 e3 frame alignment pattern. when the pattern is detected for two consecutive frames, an in- frame condition is declared. note: there is no
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 271 document id: pmc-1990267, issue 3 control transmit operation receive operation atm cell alignment with the g.832 e3 frame. therefore cell delineation must be performed to locate the atm cell boundaries. em: error monitor, bip-8 inserts the calculated bip-8 by computing even parity over all transmit bits, including the overhead bits of the previous 125 s frame. computes the incoming bip-8 value over one 125 s frame. the result is held and compared against the value in the em byte of the subsequent frame. tr: trail trace inserts the 16 byte trail access point identifier specified in internal registers. extracts the repetitive trail access point identifier and verifies that the same pattern is received. compares the received pattern to the expected pattern programmed in a register. ma: maintenance and adaptation byte inserts the ferf, febe, payload type bits, tributary unit multiframe indicator bits and the timing marker bit as programmed in a register or as indicated by detection of receive oof or bip-8 errors. extracts and reports the ferf bit value when it has been the same for 3 or five consecutive frames. s/uni-jet also extracts and accumulates febe occurrences and extracts the payload type, tributary unit multiframe, and timing market indicator bits and reports them through microprocessor accessible registers. nr: network operator byte inserts the network operator byte from the toh overhead stream or optionally from the tdpr. all 8 bits of the network operator byte are inserted from toh or from the tdpr. extracts the network operator byte and outputs it on roh or optionally terminates it in the rdlc. all 8 bits of the network operator byte are extracted and presented on roh or to the rdlc. gc: general purpose communication channel inserts the gc byte from the toh overhead stream or optionally from the tdpr block. extracts the gc byte and outputs it on roh or optionally terminates it in the rdlc block. 13.7 j2 frame format the s/uni-jet provides support for the g.704 and ntt j2 frame format. this format can be extended to allow for direct byte mapping of atm cells as specified in g.804. the j2 frame format consists of 789 bits frames each 125 us long, consisting of 96 bytes of payload, two reserved bytes, and five f-bits. the frames are grouped into five frame multiframes as shown in figure 15.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 272 document id: pmc-1990267, issue 3 figure 15 j2 frame structure ts1 ts2 ts3 ts4 ts95 ts96 ts97 ts98 1 1 0 0 m ts1 ts2 ts3 ts4 ts95 ts96 ts97 ts98 1 0 1 0 0 ts1 ts2 ts3 ts4 ts95 ts96 ts97 ts98 x1 x2 x3 a m ts1 ts2 ts3 ts4 ts95 ts96 ts97 ts98 e1 e2 e3 e4 e5 125 us 96 octets of byte inter- leaved payload 1-8 9-16 17-24 25-32 752- 760 761- 768 769- 776 777- 784 785 786 787 788 789 bit # frame 1 frame 2 frame 3 frame 4 the j2 framer decodes a unipolar or b8zs encoded signal and frames to the resulting 6,312 kbit/s j2 bit stream. once in frame, the j2 framer provides indications of frame and multiframe boundaries and marks overhead bits, x-bits, m-bits and reserved channels (ts97 and ts98). indications of los, bipolar violations, excessive zeroes, change of frame alignment, framing errors, and crc errors are provided and accumulated in internal counters. the j2 transmitter inserts the overhead bits into a j2 bit stream and produces a b8zs-encoded signal. the j2 transmitter adheres to the framing format specified in g.704 and ntt technical reference for high speed digital leased circuit services. the processing of the overhead bits in the j2 frame is described in table 41. in the transmit direction, the overhead bits can be inserted on a bit-by-bit basis from a user supplied data using the toh, tohins, tohfp, and tohclk signals. in the receive direction, the overhead bits are brought out serially on the roh data stream. table 41 j2 frame overhead operation control transmit operation receive operation ts1-ts96: byte interleaved payload inserts the atm cells into ts1 to ts96 octets. extracts the atm cell octet payload and performs cell delineation. ts97-ts98: signaling channels inserts the signaling bytes from either register bits or from the toh and tohins inputs. these bits can be optionally inserted via tdati input when in framer only mode. extracts signaling bytes on the roh output. frame alignment signal inserts the frame alignment signal automatically. finds j2 frame alignment by searching for the frame alignment signal. m-bits: 4khz data link inserts the 4 khz data link signal from the internal hdlc controller or from the bit oriented code generator. extracts the 4 khz data link signal for the internal hdlc controller.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 273 document id: pmc-1990267, issue 3 control transmit operation receive operation x-bits: spare bits inserts the spare bits via register bits or via toh and tohins input pins. extracts and presents the x-bits on register bits. the x-bit states can be debounced and presented on the roh output pin. an interrupt change can be generated to signal a change in the x-bit state. a-bit: remote lof indication inserts the a-bit via register bit. the a-bit can be optionally be asserted when the j2 framer is in lof condition. extracts and presents the a-bit on a register bit. the a-bit state can be debounced and presented on the roh output pin. an interrupt can be generated to signal a change in the a- bit state. e1-e5: crc-5 check sequence automatically calculates and inserts the crc-5 check sequence. calculates the crc-5 check sequence for the received data stream. discrepancies with the received crc-5 code can be configured to generate an interrupt. crc-5 errors are accumulated in an internal counter. 13.8 s/uni-jet cell data structure atm cells may be passed to and from the s/uni-jet using a 26-word or 27-word data structure and a 52-byte or 53-byte word data structure. these data structures are shown in figure 16, figure 17, figure 18, and figure 19. figure 16 16-bit wide, 26-byte word structure bit 15 bit 0 h1 h2 h3 h4 payload1 payload2 bit 8 bit 7 payload3 payload4 payload5 payload6 word 1 word 2 word 3 word 4 word 5 payload47 payload48 word 26
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 274 document id: pmc-1990267, issue 3 figure 17 16-bit wide, 27-byte word structure h3 h4 hcs status/control h5 payload1 payload2 payload3 payload4 payload5 payload6 bit 15 bit 0 h1 h2 bit 8 bit 7 word 1 word 2 word 3 word 4 word 5 word 6 payload47 payload48 word 27 the 16-bit sci-phy tm compliant data structure is selected when the atm8 input is tied low. bit 15 of each word is the most significant bit, which corresponds to the first bit transmitted or received. selection between the 26-byte and 27-byte word structure is done with the ds27_53 register bit in the s/uni-jet configuration 1 register. the 26-byte word structure is chosen when ds27_53 is set to logic zero. the 27-byte word structure is chosen when ds27_53 is set to logic one. the start of cell indication input and output (tsoc and rsoc) are coincident with word 1 (containing the first two header octets). the hcs octet is only passed through the 27-byte word structure. word 3 of this structure contains the hcs octet in bits 15 to 8. in the receive direction with the 27-byte word structure, the lower 8 bits of word 3 contain the hcs status octet. an all-zeros pattern in these 8 bits indicates that the associated header is error free. an all-ones pattern indicates that the header contains an uncorrectable error. (if the hcspass bit in the rxcp-50 configuration 2 register is set to logic zero, the all-ones pattern will never be passed in this structure.) an alternating ones and zeros pattern (xxaa) indicates that the header contained a correctable error. in this case the header passed through the structure is the "corrected" header. in the transmit direction, with the 27-byte word structure, the hcsb bit in the txcp-50 configuration 1 register determines whether the hcs is calculated internally or is inserted directly from the upper 8 bits of word 3. the lower 8 bits of word 3 contain the hcs control octet. the hcs control octet is an error mask that allows the insertion of one or more errors in the hcs octet. a logic one in a given bit position causes the inversion of the corresponding hcs bit position. (for example a logic one in bit 7 causes the most significant bit of the hcs to be inverted.)
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 275 document id: pmc-1990267, issue 3 with the 26-byte word structure, if the hcsb bit in the txcp-50 is logic one, then no hcs byte is inserted on the data read from the utopia interface or on the idle cells. in such a configuration, the rxcp-50 should be configured to pass the 26-word output without requiring cell delineation by setting the ccdis bit to logic one. this setting is useful for passing arbitrary payload through the transmit and receive utopia interfaces. figure 18 8-bit wide, 52-byte word structure bit 0 h1 h2 h4 bit 7 payload1 word 1 word 2 word 3 word 4 word 5 payload48 w ord 52 h3
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 276 document id: pmc-1990267, issue 3 figure 19 8-bit wide, 53-byte word structure bit 0 h1 h2 h4 bit 7 h5 payload1 word 1 word 2 word 3 word 4 word 5 word 6 payload48 w ord 53 h3 the 8-bit sci-phy tm compliant data structure is selected when the atm8 input is tied high. bit 7 of each word is the most significant bit, which corresponds to the first bit transmitted or received. selection between the 52-byte and 53-byte word data structures is done by the ds27_53 register bit in the s/uni-jet configuration 1 register. the 52-byte word structure is chosen when ds27_53 is set to logic zero. the 53-byte word structure is chosen when ds27_53 is set to logic one. the start of cell indication input and output (tsoc and rsoc) are coincident with word 1 (containing the first cell header octet). the header check sequence octet (hcs) is passed through the 53-byte word structure. word 5 of this structure contains the hcs octet. in the receive direction, cells containing "detected and uncorrected" header errors are dropped when the hcspass bit in the rxcp-50 configuration 2 register is set to logic zero. no hcs status information is passed within this data structure. cells with error free headers and "detected and corrected" headers are passed when hcspass and discor are logic zero. cells containing uncorrectable hcs errors are dropped while the hcspass bit is set to logic zero. error free headers, "detected and corrected" headers, and "detected and uncorrected" headers are passed when hcspass is a logic one. in the receive direction, idle cells are dropped when the idlepass bit in the rxcp-50 configuration 2 register is set to a logic zero. no cells are passed when the s/uni-jet is in the plcp lof defect state (for plcp based transmission), or when the s/uni-jet is in the out of cell delineation defect state (for non-plcp based transmission).
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 277 document id: pmc-1990267, issue 3 in the transmit direction, the hcsb bit in the txcp-50 configuration 1 register determines whether the hcs is calculated internally or is inserted directly from word 5. for the 52-byte word structure, if the hcsb bit in the txcp-50 is logic one, then no hcs byte is inserted and the txcp-50 will only transmit the data present on the 52 words. in such a configuration, the rxcp- 50 should be configured to pass the 52-byte word output without requiring cell delineation by setting the ccdis bit to logic one. this setting is useful for passing arbitrary payload through the transmit and receive utopia interfaces. 13.9 resetting the rxff and txff fifos resetting the receive and transmit fifos can be accomplished using the fiforst bits (rxcp- 50 fifo/utopia control & configuration, txcp-50 configuration 1 registers). when resetting, the fiforst bit should be written with a logic one, and held for two or more clock cycles (the longer of two utopia clock cycles or 16 line clock cycles). after de-asserting fiforst, data can be safely written to the txff after two or more clock cycles have passed. 13.10 servicing interrupts the s/uni-jet will assert intb to logic zero when a condition that is configured to produce an interrupt occurs. to determine the condition that caused this interrupt to occur, follow the procedure below: ? read the int bits of the s/uni-jet clock activity monitor and interrupt identification register (307h). ? read the s/uni-jet interrupt status register (005h, 105h, 205h, and 305h) to identify which block produced the interrupt. for example, a logic one on the tdpri register bit in register 305h indicates that the tdpr block of the s/uni-jet produced the interrupt. ? service the interrupt. ? if the intb pin is still logic zero, then there are still interrupts to be serviced. otherwise, all interrupts have been serviced. wait for the next assertion of intb. 13.11 using the performance monitoring features the pmon and cppm blocks are provided for performance monitoring purposes. the rxcp-50 and txcp-50 also contain performance monitor registers. the pmon block is used to monitor ds3, e3, and j2 performance primitives while the cppm is used to monitor plcp and idle-cell- based primitives. the rxcp-50 is used to monitor received cell primitives, and the txcp-50 is used to monitor transmit cell primitives. the counters in the pmon block have been sized as not to saturate if polled every second. the counters in the cppm blocks have been sized as not to saturate if polled every 1/2 second at line rates up to 44.736 mhz. the counters in the rxcp-50 and txcp-50 have been sized to not saturate if polled every second at line rates up to 44.736 mhz.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 278 document id: pmc-1990267, issue 3 the ds3, e3, and j2 primitives can be accumulated independently of the plcp and cell-based primitives. an accumulation interval is initiated by writing to one of the pmon event counter register addresses. after writing to a pmon count register, a number of rclk clock periods (three for j2 mode, 255 for ds3 mode, 500 for g.832 e3 mode, and three for g.751 e3 mode) must be allowed to elapse to permit the pmon counter values to be properly transferred. the pmon registers may then be read. plcp and cell-based primitives can be accumulated independent of the ds3, e3, or j2 primitives. an accumulation interval is initiated by writing to one of the cppm event counter register addresses. after writing to a cppm count register, a maximum of 67 rclk clock periods must be allowed to elapse to permit all the cppm values to be properly transferred. the cppm registers may then be read. the rxcp-50 and txcp-50 accumulate cell-based primitives such as received cells, corrected cell headers, uncorrected cell headers, and transmitted cells. an accumulation interval in each block is initiated by writing to one of the rxcp-50 or txcp-50 event counter register addresses. after writing to a count register, a maximum of 67 rclk or ticlk clock periods must be allowed to elapse to permit all the rxcp-50 or txcp-50 values to be properly transferred. the rxcp-50 or txcp-50 count registers may then be read. writing to the s/uni-jet identification, master reset, and global monitor update registers causes the pmon, cppm, rxcp-50, and txcp-50 performance event counters to latch and a new accumulation period to start in all four quadrants of the s/uni-jet. a maximum of 67 rclk clock periods must be allowed to elapse to permit all the event count registers to be properly transferred. 13.12 using the internal pmdl transmitter note: the access rate to the tdpr registers is limited by the rate of the internal high-speed system clock selected by the linesysclk register bit of the s/uni-jet miscellaneous register (39bh). consecutive accesses to the tdpr configuration, tdpr interrupt status/udr clear, and tdpr transmit data registers should be accessed (with respect to wrb rising edge and rdb falling edge) at a rate no faster than 1/8 that of the selected tdpr high-speed system clock. this time is used by the high-speed system clock to sample the event, write the fifo, and update the fifo status. instantaneous variations in the high-speed reference clock frequencies (e.g. jitter in the line clock) must be considered when determining the procedure used to read and write the tdpr registers. upon reset of the s/uni-jet , the tdpr should be disabled by setting the en bit in the tdpr configuration register to logic zero (default value). an hdlc all-ones idle signal will be sent while in this state. the tdpr is enabled by setting the en bit to logic one. the fifoclr bit should be set and then cleared to initialize the tdpr fifo. the tdpr is now ready to transmit.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 279 document id: pmc-1990267, issue 3 to initialize the tdpr, the tdpr configuration register must be properly set. if fcs generation is desired, the crc bit should be set to logic one. if the block is to be used in interrupt driven mode, then interrupts should be enabled by setting the fulle, ovre, udre, and lfille bits in the tdpr interrupt enable register to logic one. the tdpr operating parameters in the tdpr upper transmit threshold and tdpr lower interrupt threshold registers should be set to the desired values. the tdpr upper transmit threshold sets the value at which the tdpr automatically begins the transmission of hdlc packets, even if no complete packets are in the fifo. transmission will continue until current packet is transmitted and the number of bytes in the tdpr fifo falls to, or below, this threshold level. the tdpr will always transmit all complete hdlc packets (packets with eom attached) in its fifo. finally, the tdpr can be enabled by setting the en bit to logic one. if no message is sent after the en bit is set to logic one, continuous flags will be sent. the tdpr can be used in a polled or interrupt driven mode for the transfer of data. in the polled mode the processor controlling the tdpr must periodically read the tdpr interrupt status register to determine when to write to the tdpr transmit data register. in the interrupt driven mode, the processor controlling the tdpr uses the intb output, the s/uni-jet clock activity monitor and interrupt identification register, and the s/uni-jet interrupt status register to identify tdpr interrupts which determine when writes can or must be done to the tdpr transmit data register. 13.12.1 interrupt driven mode the tdpr automatically transmits a packet once it is completely written into the tdpr fifo. the tdpr also begins transmission of bytes once the fifo level exceeds the programmable upper transmit threshold. the crc bit can be set to logic one so that the fcs is generated and inserted at the end of a packet. the tdpr lower interrupt threshold should be set to such a value that sufficient warning of an underrun is given. the fulle, lfille, ovre, and udre bits are all set to logic one so an interrupt on intb is generated upon detection of a fifo full state, a fifo depth below the lower limit threshold, a fifo overrun, or a fifo underrun. use the following procedure to transmit hdlc packets: ? wait for data to be transmitted. once data is available to be transmitted, then go to step 2. ? write the data byte to the tdpr transmit data register. ? if all bytes in the packet have been sent, then set the eom bit in the tdpr configuration register to logic one. go to step 1. ? if there are more bytes in the packet to be sent, then go to step 2. while performing steps 1 to 3, the processor should monitor for interrupts generated by the tdpr. when an interrupt is detected, the tdpr interrupt routine, described in the following section, should be immediately followed.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 280 document id: pmc-1990267, issue 3 the tdpr will force transmission of the packet information when the fifo depth exceeds the threshold programmed with the uthr[6:0] bits in the tdpr upper transmit threshold register. unless an error condition occurs, transmission will not stop until the last byte of all complete packets is transmitted and the fifo depth is at or below the threshold limit. the user should watch the fulli and lfilli interrupts to prevent overruns and underruns. 13.12.2 tdpr interrupt routine upon assertion of intb, the source of the interrupt must first be identified by reading the s/uni- jet clock activity monitor and interrupt identification register (007h) and the s/uni-jet interrupt status registers (005h, 105h, 205h, 305h). once the source of the interrupt has been identified as tdpr, do the following procedure: ? read the tdpr interrupt status register. ? if udri=1, then the fifo has underrun and the last packet transmitted has been corrupted and needs to be retransmitted. when the udri bit transitions to logic one, one abort sequence and continuous flags will be transmitted. the tdpr fifo is held in reset state. to reenable the tdpr fifo and to clear the underrun, the tdpr interrupt status/udr clear register should be written with any value. ? if ovri=1, then the fifo has overflowed. the packet which the last byte written into the fifo belongs to has been corrupted and must be retransmitted. other packets in the fifo are not affected. either a timer can be used to determine when sufficient bytes are available in the fifo or the user can wait until the lfilli interrupt is set, indicating that the fifo depth is at the lower threshold limit. if the fifo overflows on the packet currently being transmitted (packet is greater than 128 bytes long), ovri is set, an abort signal is scheduled to be transmitted, the fifo is emptied, and then flags are continuously sent until there is data to be transmitted. the fifo is held in reset until a write to the tdpr transmit data register occurs. this write contains the first byte of the next packet to be transmitted. if fulli=1 and full=1, then the tdpr fifo is full and no further bytes can be written. when in this state, either a timer can be used to determine when sufficient bytes are available in the fifo or the user can wait until the lfilli interrupt is set, indicating that the fifo depth is at the lower threshold limit. if fulli=1 and full=0, then the tdpr fifo had reached the full state earlier, but has since emptied out some of its data bytes and now has space available in its fifo for more data. if lfilli=1 and blfill=1, then the tdpr fifo depth is below its lower threshold limit. if there is more data to transmit, then it should be written to the tdpr transmit data register before an underrun occurs. if there is no more data to transmit, then an eom should be set at the end of the last packet byte. flags will then be transmitted once the last packet has been transmitted. if lfilli=1 and blfill=0, then the tdpr fifo had fallen below the lower-threshold state earlier, but has since been refilled to a level above the lower-threshold level.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 281 document id: pmc-1990267, issue 3 polling mode the tdpr automatically transmits a packet once it is completely written into the tdpr fifo. the tdpr also begins transmission of bytes once the fifo level exceeds the programmable upper transmit threshold. the crc bit can be set to logic one so that the fcs is generated and inserted at the end of a packet. the tdpr lower interrupt threshold should be set to such a value that sufficient warning of an underrun is given. the fulle, lfille, ovre, and udre bits are all set to logic zero since packet transmission is set to work with a periodic polling procedure. to transmit hdlc packets: ? wait until data is available to be transmitted, then go to step 2. ? read the tdpr interrupt status register. ? if full=1, then the tdpr fifo is full and no further bytes can be written. continue polling the tdpr interrupt status register until either full=0 or blfill=1. then, go to either step 4 or 5 depending on implementation preference. ? if blfill=1, then the tdpr fifo depth is below its lower threshold limit. write the data into the tdpr transmit data register. go to step 6. ? if full=0, then the tdpr fifo has room for at least 1 more byte to be written. write the data into the tdpr transmit data register. go to step 6. ? if more data bytes are to be transmitted in the packet, then go to step 2. ? if all bytes in the packet have been sent, then set the eom bit in the tdpr configuration register to logic one. go to step 1. 13.13 using the internal data link receiver note: the access rate to the rdlc registers is limited by the rate of the internal high-speed system clock selected by the linesysclk register bit of the s/uni-jet miscellaneous registers (09bh, 19bh, 29bh, 39bh). consecutive accesses to the rdlc status and rdlc data registers should be accessed at a rate no faster than 1/10 that of the selected rdlc high- speed system clock. this time is used by the high-speed system clock to sample the event and update the fifo status. instantaneous variations in the high-speed reference clock frequencies (e.g. jitter in the receive line clock) must be considered when determining the procedure used to read rdlc registers. on power up of the system, the rdlc should be disabled by setting the en bit in the configuration register to logic zero (default state). the rdlc interrupt control register should then be initialized to enable the int output and to select the fifo buffer fill level at which an interrupt will be generated. if the inte bit is not set to logic one, the rdlc status register must be continuously polled to check the interrupt status (intr) bit.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 282 document id: pmc-1990267, issue 3 after the rdlc interrupt control register has been written, the rdlc can be enabled at any time by setting the en bit in the rdlc configuration register to logic one. when the rdlc is enabled, it will assume the link status is idle (all ones) and immediately begin searching for flags. when the first flag is found, an interrupt will be generated, and a dummy byte will be written into the fifo buffer, which provides alignment of link up status with the data read from the fifo. when an abort character is received, another dummy byte and link down status is written into the fifo, which provides alignment of link down status with the data read from the fifo. it is up to the controlling processor to check the cols bit in the rdlc status register for a change in the link status. if the cols bit is set to logic one, the fifo must be emptied to determine the current link status. the first flag and abort status encoded in the pbs bits are used to set and clear a link active software flag. when the last byte of a properly terminated packet is received, an interrupt is generated. while the rdlc status register is being read the pkin bit will be logic one. this can be a signal to the external processor to empty the bytes remaining in the fifo or to just increment a number-of- packets-received count and wait for the fifo to fill to a programmable level. once the rdlc status register is read, the pkin bit is cleared to logic zero. if this register is read immediately after the last packet byte is read from the fifo, the pbs[2] bit will be logic one and the crc and non-integer byte status can be checked by reading the pbs[1:0] bits. when the fifo fill level is exceeded, an interrupt is generated. the fifo must be emptied to remove this source of interrupt. the rdlc can be used in a polled or interrupt driven mode for the transfer of frame data. in the polled mode, the processor controlling the rdlc must periodically read the rdlc status register to determine when to read the rdlc data register. in the interrupt driven mode, the processor controlling the rdlc uses the s/uni-jet intb output, the s/uni-jet clock activity monitor and interrupt identification register, and the s/uni-jet interrupt status registers to determine when to read the rdlc data register. in the case of interrupt driven data transfer from the rdlc to the processor, the intb output of the s/uni-jet is connected to the interrupt input of the processor. the processor interrupt service routine verifies what block generated the interrupt by reading the s/uni-jet clock activity monitor and interrupt identification register, and the s/uni-jet interrupt status registers. once it has identified that the rdlc has generated the interrupt, it processes the data in the following order: ? reads the rdlc status register. the intr bit should be logic one. if ovr = 1, then discards last frame and go to step 1. overrun causes a reset of fifo pointers. any packets that may have been in the fifo are lost. if cols = 1, then sets the empty fifo software flag. if pkin = 1, increments the packet count. if the fifo is desired to be emptied as soon as a complete packet is received, set the empty fifo software flag. if the empty fifo software flag is not set, fifo emptying will delayed until the fifo fill level is exceeded. ? reads the rdlc data register. ? reads the rdlc status register.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 283 document id: pmc-1990267, issue 3 if ovr = 1, then discards last frame and go to step 1. overrun causes a reset of fifo pointers. any packets that may have been in the fifo are lost. if cols = 1, then sets the empty fifo software flag. if pkin = 1, increments the packet count. if the fifo is desired to be emptied as soon as a complete packet is received, set the empty fifo software flag. if the empty fifo software flag is not set, fifo emptying will delayed until the fifo fill level is exceeded. ? starts the processing of fifo data. uses the pbs[2:0] packet byte status bits to decide what is to be done with the fifo data. if pbs[2:0] = 001, discards data byte read in step 3 and sets the link active software flag. if pbs[2:0] = 010, discards the data byte read in step 3 and clears the link active software flag. if pbs[2:0] = 1xx, stores the last byte of the packet, decrements the packet count, and checks the pbs[1:0] bits for crc or nvb errors before deciding whether or not to keep the packet. if pbs[2:0] = 000, stores the packet data. if fe = 0 and intr = 1 or fe = 0 and empty fifo = 1, goes to step 3 or else clears the empty fifo software flag and leaves this interrupt service routine to wait for the next interrupt. the link state is typically a local software variable. the link state is inactive if the rdlc is receiving all-ones or receiving bit-oriented codes which contain a sequence of eight ones. the link state is active if the rdlc is receiving flags or data. if the rdlc data transfer is operating in the polled mode, processor operation is exactly as shown above for the interrupt driven mode, except that the entry to the service routine is from a timer, rather than an interrupt.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 284 document id: pmc-1990267, issue 3 figure 20 typical data frame 8765432 1 0111111 0 flag address (high) (low) control frame check sequence 0111111 0 flag data bytes written to the transmit data register and serially transmitted, bit 1 first bit: appended after eom is set, if crc is set bit 1 is the first serial bit to be received. when enabled, the primary, secondary and universal addresses are compared with the high order packet address to determine a match. figure 21 shows the timing of interrupts, the state of the fifo, and the state of the data link relative the input data sequence. the cause of each interrupt and the processing required at each point is described in the following paragraphs. figure 21 example multi-packet operational sequence data int fe la 12 345 67 f f f fa d d d dd d d d d ddddd f f f fd d d dff notes 1. f is the flag sequence (01111110). 2. a is the abort sequence (01111111). 3. d is the packet data bytes. 4. int is the active high interrupt output.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 285 document id: pmc-1990267, issue 3 5. fe is the internal fifo empty status. 6. la is the state of the link active software flag. at points 1 and 5 the first flag after all-ones or abort is detected. a dummy byte is written in the fifo, fe goes low, and an interrupt goes high. when the interrupt is detected by the processor it reads the dummy byte, the fifo becomes empty, and the interrupt is removed. the link active (la) software flag is set to logic one. at points 2 and 6 the last byte of a packet is detected and interrupt goes high. when the interrupt is detected by the processor, it reads the data and status registers until the fifo becomes empty. the interrupt is removed as soon as the rdlc status register is read since the fifo fill level of 8 bytes has not been exceeded. it is possible to store many packets in the fifo and empty the fifo when the fifo fill level is exceeded. in either case the processor should use this interrupt to count the number of packets written into the fifo. the packet count or a software time-out can be used as a signal to empty the fifo. at point 3 the fifo fill level of 8 bytes is exceeded and interrupt goes high. when the interrupt is detected by the processor it must read the data and status registers until the fifo becomes empty and the interrupt is removed. at points 4 or 7 an abort character is detected, a dummy byte is written into the fifo, and interrupt goes high. when the interrupt is detected by the processor it must read the data and status registers until the fifo becomes empty and the interrupt is removed. the link active software flag is cleared. 13.14 prgd pattern generation a pseudo-random or repetitive pattern can be inserted or extracted in the plcp payload (if plcp framing is enabled) or in the ds3, e3, j2, or arbitrary framing format payload (if plcp framing is disabled). it cannot be inserted into the atm cell payload. the pattern generator can be configured to generate pseudo random patterns or repetitive patterns as shown in figure 22: figure 22 prgd pattern generator 123 32 length ps tap
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 286 document id: pmc-1990267, issue 3 the pattern generator consists of a 32-bit shift register and a single xor gate. the xor gate output is fed into the first stage of the shift register. the xor gate inputs are determined by values written to the length register (pl[4:0]) and the tap register (pt[4:0], when the ps bit is low). when ps is high, the pattern detector functions as a recirculating shift register, with length determined by pl[4:0]. 13.14.1 generating and detecting repetitive patterns when a repetitive pattern (such as 1-in-8) is to be generated or detected, the ps bit must be set to logic one. the pattern length register must be set to (n-1), where n is the length of the desired repetitive pattern. several examples of programming for common repetitive sequences are given below in the common test patterns section. for pattern generation, the desired pattern must be written into the prgd pattern insertion registers. the repetitive pattern will then be continuously generated. the generated pattern will be inserted in the output data stream, but the phase of the pattern cannot be guaranteed. for pattern detection, the prgd will determine if a repetitive pattern of the length specified in the pattern length register exists in the input stream. it does so by loading the first n bits from the data stream, and then monitoring to see if the pattern loaded repeats itself error free for the subsequent 48-bit periods. it will repeat this process until it finds a repetitive pattern of length n, at which point it begins counting errors (and possibly re-synchronizing) in the same way as for pseudo-random sequences. note: the prgd does not look for the pattern loaded into the pattern insertion registers, but rather automatically detects any repetitive pattern of the specified length. the precise pattern detected can be determined by initiating a prgd update, setting pdr[1:0] = 00 in the prgd control register, and reading the pattern detector registers, which will then contain the 32 bits detected immediately prior to the strobe. 13.14.2 common test patterns the prgd can be configured to monitor the standardized pseudo random and repetitive patterns described in itu-t o.151. the register configurations required to generate these patterns and others are indicated in the table 42 and table 43. table 42 pseudo random pattern generation (ps bit = 0) pattern type tr lr ir#1 ir#2 ir#3 ir#4 tinv rinv 2 3 -1 00 02 ff ff ff ff 0 0 2 4 -1 00 03 ff ff ff ff 0 0 2 5 -1 01 04 ff ff ff ff 0 0 2 6 -1 04 05 ff ff ff ff 0 0 2 7 -1 00 06 ff ff ff ff 0 0 2 7 -1 (fractional t1 lb activate) 03 06 ff ff ff ff 0 0
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 287 document id: pmc-1990267, issue 3 2 7 -1 (fractional t1 lb deactivate) 03 06 ff ff ff ff 1 1 2 9 -1 (o.153) 04 08 ff ff ff ff 0 0 2 10 -1 02 09 ff ff ff ff 0 0 2 11 -1 (o.152, o.153) 08 0a ff ff ff ff 0 0 2 15 -1 (o.151) 0d 0e ff ff ff ff 1 1 2 17 -1 02 10 ff ff ff ff 0 0 2 18 -1 06 11 ff ff ff ff 0 0 2 20 -1 (o.153) 02 13 ff ff ff ff 0 0 2 20 -1 (o.151 qrss bit=1) 10 13 ff ff ff ff 0 0 2 21 -1 01 14 ff ff ff ff 0 0 2 22 -1 00 15 ff ff ff ff 0 0 2 23 -1 (o.151) 11 16 ff ff ff ff 1 1 2 25 -1 02 18 ff ff ff ff 0 0 2 28 -1 02 1b ff ff ff ff 0 0 2 29 -1 01 1c ff ff ff ff 0 0 2 31 -1 02 1e ff ff ff ff 0 0 table 43 repetitive pattern generation (ps bit = 1) pattern type tr lr ir#1 ir#2 ir#3 ir#4 tinv rinv all ones 00 00 ff ff ff ff 0 0 all zeros 0000feffffff0 0 alternating ones/zeros 00 01 fe ff ff ff 0 0 double alternating ones/zeros 00 03 fc ff ff ff 0 0 3 in 24 00 17 22 00 20 ff 0 0 1 in 16 00 0f 01 00 ff ff 0 0 1 in 8 000701 ffffff0 0 1 in 4 0003f1ffffff0 0 inband loopback activate 00 04 f0 ff ff ff 0 0 inband loopback deactivate 00 02 fc ff ff ff 0 0 notes (for the pseudo random and repetitive pattern generation tables) 1. the ps bit and the qrss bit are contained in the prgd control register 2. tr is the prgd tap register 3. lr is the prgd length register 4. ir#1 is the prgd pattern insertion #1 register 5. ir#2 is the prgd pattern insertion #2 register
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 288 document id: pmc-1990267, issue 3 6. ir#3 is the prgd pattern insertion #3 register 7. ir#4 is the prgd pattern insertion #4 register 8. the tinv bit and the rinv bit are contained in the prgd control register 13.15 jtag support the s/uni-jet supports the ieee boundary scan specification as described in the ieee 1149.1 standards. the tap consists of the five standard pins (trstb, tck, tms, tdi, and tdo) used to control the tap controller and the boundary scan registers. the trstb input is the active-low reset signal used to reset the tap controller. tck is the test clock used to sample data on input, tdi and to output data on output, tdo. the tms input is used to direct the tap controller through its states. the basic boundary scan architecture is shown in figure 23. figure 23 boundary scan architecture boundary scan register control tdi tdo device identification register bypass register instruction register and decode trstb tms test access port controller mux dff select tri-state enable tck
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 289 document id: pmc-1990267, issue 3 the boundary scan architecture consists of: ? a tap controller. ? an instruction register with instruction decode. ? a bypass register ? a device identification register ? a boundary scan register. the tap controller interprets the tms input and generates control signals to load the instruction and data registers. the instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. the bypass register offers a single-bit delay from primary input, tdi to primary output, tdo. the device identification register contains the device identification code. the boundary scan register allows testing of board inter-connectivity. the boundary scan register consists of a shift register place in series with device inputs and outputs. using the boundary scan register, all digital inputs can be sampled and shifted out on primary output, tdo. in addition, patterns can be shifted in on primary input, tdi and forced onto all digital outputs. 13.15.1 tap controller the tap controller is a synchronous finite state machine clocked by the rising edge of primary input, tck. all state transitions are controlled using primary input, tms. the finite state machine is described below.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 290 document id: pmc-1990267, issue 3 figure 24 tap controller finite state machine trstb=0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 all transitions dependent on input tms 0 0 0 0 0 1 select-dr- scan capture- dr shift- dr test-logic- reset run-test- idle exit1- dr pause- dr exit2- dr select-ir- scan capture- ir shift- ir exit1- ir pause- ir exit2- ir update- ir update- dr test-logic-reset
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 291 document id: pmc-1990267, issue 3 the test logic reset state is used to disable the tap logic when the device is in normal mode operation. the state is entered asynchronously by asserting input, trstb. the state is entered synchronously regardless of the current tap controller state by forcing input, tms high for 5 tck clock cycles. while in this state, the instruction register is set to the idcode instruction. run-test-idle the run test/idle state is used to execute tests. capture-dr the capture data register state is used to load parallel data into the test data registers selected by the current instruction. if the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. loading occurs on the rising edge of tck. shift-dr the shift data register state is used to shift the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck. update-dr the update data register state is used to load a test register's parallel output latch. in general, the output latches are used to control the device. for example, for the extest instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. the parallel output latches are updated on the falling edge of tck. capture-ir the capture instruction register state is used to load the instruction register with a fixed instruction. the load occurs on the rising edge of tck. shift-ir the shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck. update-ir the update instruction register state is used to load a new instruction into the instruction register. the new instruction must be scanned in using the shift-ir state. the load occurs on the falling edge of tck. the pause-dr and pause-ir states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused. boundary scan instructions
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 292 document id: pmc-1990267, issue 3 the following is an description of the standard instructions. each instruction selects an serial test data register path between input, tdi and output, tdo. bypass the bypass instruction shifts data from input, tdi to output, tdo with one tck clock period delay. the instruction is used to bypass the device. extest the external test instruction allows testing of the interconnection to other devices. when the current instruction is the extest instruction, the boundary scan register is place between input, tdi and output, tdo. primary device inputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. primary device outputs can be controlled by loading patterns shifted in through input tdi into the boundary scan register using the update-dr state. sample the sample instruction samples all the device inputs and outputs. for this instruction, the boundary scan register is placed between tdi and tdo. primary device inputs and outputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. idcode the identification instruction is used to connect the identification register between tdi and tdo. the device's identification code can then be shifted out using the shift-dr state. stctest the single transport chain instruction is used to test out the tap controller and the boundary scan register during production test. when this instruction is the current instruction, the boundary scan register is connected between tdi and tdo. during the capture-dr state, the device identification code is loaded into the boundary scan register. the code can then be shifted out output, tdo using the shift-dr state. boundary scan cell description in the following diagrams, clock-dr is equal to tck when the current controller state is shift-dr or capture-dr, and unchanging otherwise. the multiplexer in the center of the diagram selects one of four inputs, depending on the status of select lines g1 and g2. the id code bit is as listed in the boundary scan register table located in the test features description - jtag test port section.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 293 document id: pmc-1990267, issue 3 figure 25 input observation cell (in_cell) input pad d c clock-dr scan chain out input to internal logic shift-dr scan chain in 1 2 mux 1 2 1 2 1 2 i.d. code bit idcode g1 g2 figure 26 output cell (out_cell) d c d c g1 g2 1 2 mux g1 1 1 mux output or enable from system logic scan chain in scan chain out extest output or enable shift-dr clock-dr update-dr 1 2 1 2 1 2 idcode i.d. code bit
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 294 document id: pmc-1990267, issue 3 figure 27 bi-directional cell (io_cell) d c d c g1 1 1 mux output from internal logic scan chain in scan chain out extest output to pin shift-dr clock-dr update-dr input from pin input to internal logic g1 1 2 mux 1 2 1 2 1 2 g2 idcode i.d. code bit figure 28 layout of output enable and bi-directional cells output enable from internal logic (0 = drive) input to internal logic output from internal logic scan chain in scan chain out i/o pad out_cell io_cell
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 295 document id: pmc-1990267, issue 3 14 functional timing all functional timing diagrams assume that polarity control is not being applied to input and output data and clock lines (i.e. polarity control bits in the s/uni-jet registers are set to their default states). figure 29 receive ds1 stream rclk rdati f bit rohm info 4 info 192 f bit info 1 info 2 info 3 info 4 info 5 info 3 info 1 info 2 the receive ds1 stream diagram (figure 29) shows the expected ds1 overhead indicators on rohm when the s/uni-jet is configured for ds1 plcp or ds1 direct-mapped frame formats. frame pulses on rohm are not required to be present. once internally synchronized by a pulse on rohm, the s/uni-jet can use its internal timeslot counter for ds1 overhead bit identification. the atm cell stream is contained in rdati, along with a framing bit placeholder every 193 bit periods. an upstream ds1 framer (such as the pm4341a t1xc or pm4344 tquad) must be used to identify the ds1 framing bit position. figure 30 receive e1 stream rclk rdati ts0 bit1 rohm ts0 bit5 ts31 bit8 ts0 bit1 ts0 bit2 ts0 bit3 ts0 bit4 ts0 bit5 ts0 bit6 ts0 bit4 ts0 bit2 ts0 bit3 the expected receive e1 stream for direct-mapped or plcp applications is shown in figure 30. frame pulses on rohm are not required to be present every frame. once internally synchronized by a pulse on rohm, the s/uni-jet can use its internal timeslot counter for e1 overhead bit identification. the atm cell stream is contained in rdati, along with a framing bit placeholder every 256 bit periods. an upstream e1 framer (such as the pm6341a e1xc or pm6344 equad) must be used to identify the e1 framing bit position.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 296 document id: pmc-1990267, issue 3 figure 31 receive bipolar ds3 stream rpos rneg 3 consec 0s lcv rclk the receive bipolar ds3 stream diagram (figure 31) shows the operation of the s/uni-jet while processing a b3zs encoded ds3 stream on inputs rpos and rneg. it is assumed that the first bipolar violation (on rneg) illustrated corresponds to a valid b3zs signature. a lcv is declared upon detection of three consecutive zeros in the incoming stream, or upon detection of a bipolar violation which is not part of a valid b3zs signature. figure 32 receive unipolar ds3 stream rclk rdati x1 bit rlcv x2 bit info 84 c bit info 1 info 2 info 3 info 4 info 5 or p or m bit or f bit info 84 info 1 lcv indication the receive unipolar ds3 stream diagram (figure 32) shows the complete ds3 receive signal on the rdati input. lcv indications, detected by an upstream b3zs decoder, are indicated on input rlcv. rlcv is sampled each bit period. the pmon lcv event counter is incremented each time a logic one is sampled on rlcv. figure 33 receive bipolar e3 stream rclk rpos rneg 4 consec 0s lcv x 00v hdb3 signature pattern 000v bv 00
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 297 document id: pmc-1990267, issue 3 the receive bipolar e3 stream diagram (figure 33) shows the operation of the s/uni-jet while processing an hdb3-encoded e3 stream on inputs rpos and rneg. it is assumed that the first bipolar violation (on rneg) illustrated corresponds to a valid hdb3 signature. a lcv is declared upon detection of four consecutive zeros in the incoming stream, or upon detection of a bipolar violation which is not part of a valid hdb3 signature. figure 34 receive unipolar e3 stream rclk rdati fa1 1 rlcv info x+1 info n info n+1 info n+2 info n+3 info n+4 info n+5 info n+6 info x fa1 2 lcv indication the receive unipolar e3 stream diagram (figure 34) shows the unipolar e3 receive signal on the rdati input. lcv indications, detected by an upstream hdb3 decoder, are indicated on input rlcv. rlcv is sampled each bit period. the pmon lcv event counter is incremented each time a logic one is sampled on rlcv. figure 35 receive bipolar j2 stream b8zs signature 000v10v1 rclk rneg rpos 000 0 v000 00 01 00 0 8zeros lcv exz the receive bipolar j2 stream diagram (figure 35) shows the operation of the s/uni-jet while processing a b8zs-encoded j2 stream on inputs rpos and rneg. it is assumed that the first bipolar violation (on rneg) illustrated corresponds to a valid b8zs signature. a lcv is declared upon detection of a bipolar violation which is not part of a valid b8zs signature. an excessive zeros indication is given when 8 or more consecutive zeros are detected.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 298 document id: pmc-1990267, issue 3 figure 36 receive unipolar j2 stream rclk rdati e 1 rlcv info x+1 info n info n+1 info n+2 info n+3 info n+4 info n+5 info n+6 info x e 2 lcv indication the receive unipolar j2 stream diagram (figure 36) shows the unipolar j2 receive signal on the rdati input. lcv indications, detected by an upstream b8zs decoder, are indicated on input rlcv. rlcv is sampled each bit period. the pmon lcv event counter is incremented each time a logic one is sampled on rlcv. figure 37 generic receive stream rclk rdati overhead bit 1 rohm info 1 info 2 info 3 info 4 info 5 overhead bit 4 overhead bit 3 overhead bit 2 overhead bit 5 overhead bit 8 overhead bit 7 overhead bit 6 the generic receive stream diagram (figure 37) illustrates how rohm is used to mark the location of the transmission system overhead bits in the rdati stream. rdati and rohm are both sampled on the rising edge of rclk.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 299 document id: pmc-1990267, issue 3 figure 38 receive ds3 overhead rohfp rohclk rohclk roh rohfp x1 unused c1 unused c2 unused c3 ds3 m-frame period the receive ds3 overhead diagram (figure 38) shows the extraction of the ds3 overhead bits on the roh output, along with overhead clock (rohclk), and m-frame position indicator (rohfp). the ds3 m-frame can be divided into seven m-subframes, with each subframe containing eight overhead bits. the table below illustrates the overhead bit order on roh: table 44 ds3 receive overhead bits ds3 overhead bits m-subframe 12345678 1 x 1 n/u c 1 n/u c 2 n/u c 3 n/u 2 x 2 n/u c 1 n/u c 2 n/u c 3 n/u 3p 1 n/u c 1 n/u c 2 n/u c 3 n/u 4p 2 n/u c 1 n/u c 2 n/u c 3 n/u 5 m 1 n/u c 1 n/u c 2 n/u c 3 n/u 6 m 2 n/u c 1 n/u c 2 n/u c 3 n/u 7 m 3 n/u c 1 n/u c 2 n/u c 3 n/u the ds3 framing bits (f-bits) are not extracted on the overhead port. the bit positions corresponding to the f-bits in the extracted stream are marked n/u in the above table. the roh stream is invalid when the ds3 frame alignment is lost.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 300 document id: pmc-1990267, issue 3 figure 39 receive g.832 e3 overhead rohclk rohfp rohclk roh g.832 frame period rohfp roh bit 1 em b y te fa1 fa2 em tr ma nr gc bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 f a 2b y te f a 1 b y te fa1fa2 54 cycles bit 1 bit 2 the receive g.832 e3 overhead diagram (figure 39) shows the extraction of the g.832 e3 overhead bits on the roh output, along with overhead clock (rohclk), and frame position indicator (rohfp). figure 40 receive g.751 e3 overhead rohfp rohclk roh g.751 frame period rai nat c11 c21 c31 c41 c12 c22 c32 c13 c23 c33 j1 j2 j3 c42 c43 j4 rai rai ... ... 30 cycles j4 ... justification service bits and tributary justification bits out p ut if pyld&just bit e q uals 0 the receive g.751 e3 overhead diagram (figure 40) shows the extraction of the g.751 e3 overhead bits on the roh output, along with overhead clock (rohclk), and frame position indicator (rohfp). the justification indication bits (c jk ) along with the justification opportunity bits (j 1 -j 4 ) are extracted when they are treated as overhead (pyld&just bit in the e3 frmr maintenance options register set to logic zero).
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 301 document id: pmc-1990267, issue 3 figure 41 receive j2 overhead the receive j2 overhead diagram (figure 41) shows the extraction of the j2 overhead bits on the roh output, along with overhead clock (rohclk), and frame position indicator (rohfp). rohclk is a gapped clock with a maximum instantaneous rate equal to the rclk frequency. rohfp pulses on the first bit of ts97 in the first frame of each j2 multiframe. figure 42 receive plcp overhead rpohfp rpohclk f1 octe t m1 octe t m2 octe t g1 octe t b1 octe t z1 octe t z2 octe t rpohclk b 5 b 4 b 6 b 3 b 7 b 2 b 1 rpoh b 5 b 4 b 6 b 3 b 7 b 2 b 8 b 1 b 8 b 8 b 1 rpohfp f1 octet b1 octet ts97 ts98 f-bits ts1 0123456701234567 1 1 0 0 m x x frame 1 frames 2, 3, 4 rclk roh rohfp rohclk
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 302 document id: pmc-1990267, issue 3 the receive plcp overhead diagram (figure 42) shows the extraction of the plcp path overhead bits on the rpoh output, along with overhead clock (rpohclk), and plcp frame position indicator (rpohfp). the path overhead octets are shifted out in order with the most significant bit (bit 1) of each octet first. the number of growth octets (zn) in the plcp frame varies according to the selected plcp frame format (ds3, ds1, g.751 e3, or e1). the plcp frame position indicator (rpohfp) is set high once per plcp frame period, during bit 1 of the f1 octet, and indicates the 8 khz receive plcp frame timing. figure 43 transmit ds1 stream tclk] tdato octet 1 bit 1 tohm overhead slot framing position octet 1 bit 1 octet 24 bit 8 octet 24 bit 7 octet 24 bit 6 octet 24 bit 5 ticlk the transmit ds1 stream diagram (figure 43) illustrates the generation of ds1 overhead indicators on tohm when the s/uni-jet is configured for ds1 plcp or non-plcp frame formats. the s/uni-jet flywheels using its internal timeslot counter to generate tohm. the atm cell stream is inserted in tdato, along with a framing bit placeholder every 193 bit periods. an upstream ds1 framer (such as the pm4341a t1xc or pm4344 tquad) must be used to insert the appropriate ds1 framing pattern. note: tclk is a flow through version of ticlk; a variable propagation delay exists between these two signals. figure 44 transmit e1 stream tclk tdato tohm ts0 bit 1 ticlk ts0 bit 2 ts31 bit 8 ts31 bit 7 ts31 bit 6 ts31 bit 5 ts0 bit 2 ts0 bit 1
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 303 document id: pmc-1990267, issue 3 the transmit e1 stream diagram (figure 44) illustrates the generation of e1 frame alignment indicators on tohm when the s/uni-jet is configured for e1 plcp or non-plcp frame formats. the s/uni-jet flywheels using its internal timeslot counter to generate tohm. the atm cell stream is inserted in tdato, along with a framing bit placeholder every 256 bit periods. an upstream e1 framer (such as the pm6341a e1xc or pm6344 equad) must be used to insert the appropriate e1 framing pattern. note: tclk is a flow through version of ticlk; a variable propagation delay exists between these two signals. figure 45 transmit bipolar ds3 stream tclk tpos tneg ticlk 11 0 01 0 0 the transmit bipolar ds3 stream diagram (figure 45) illustrates the generation of a bipolar ds3 stream. the b3zs encoded ds3 stream is present on tpos and tneg. these outputs, along with the transmit clock, tclk, can be directly connected to a ds3 line interface unit. note: tclk is a flow through version of ticlk; a variable propagation delay exists between these two signals. figure 46 transmit unipolar ds3 stream tclk tdato nib 1 bit 4 tohm ticlk x1 x1 nib 1 bit 4 nib 1190 bit 1 nib 22 bit 4 x2 nib 21 bit 1 the transmit unipolar ds3 stream diagram (figure 46) illustrates the unipolar ds3 stream generation. the atm cell stream, along with valid ds3 overhead bits is contained in tdato. the tohm output marks the m-frame boundary (the x1 bit) in the transmit stream. note: tclk is a flow through version of ticlk; a variable propagation delay exists between these two signals.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 304 document id: pmc-1990267, issue 3 figure 47 transmit bipolar e3 stream tclk tpos tneg x 00v hdb3 signature pattern 000v bv 00 ticlk the transmit bipolar e3 stream diagram (figure 47) illustrates the generation of a bipolar e3 stream. the hdb3 encoded e3 stream is present on tpos and tneg. these outputs, along with the transmit clock, tclk, can be directly connected to a e3 line interface unit. note: tclk is a flow through version of ticlk; a variable propagation delay exists between these two signals. figure 48 transmit unipolar e3 stream tclk tdato info x info x+1 tohm bip[0] bip[1] bip[2] bip[3] bip[4] bip[5] ticlk fa1 2 fa1 1 info x+465 fa1 3 the transmit unipolar e3 stream diagram (figure 48) illustrates the unipolar e3 stream generation. the atm cell stream, along with valid e3 overhead bits is contained in tdato. the tohm output shown marks the g.832 frame boundary (the first bit of the fa1 frame alignment byte) in the transmit stream. note: tclk is a flow through version of ticlk; a variable propagation delay exists between these two signals.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 305 document id: pmc-1990267, issue 3 figure 49 transmit bipolar j2 stream tclk b8zs signature 000v10v1 000 0 1000 00 11 00 0 tneg tpos ticlk the transmit bipolar j2 stream diagram (figure 49) illustrates the generation of a bipolar j2 stream. the b8zs encoded j2 stream is present on tpos and tneg. these outputs, along with the transmit clock, tclk, can be directly connected to a j2 line interface unit. note: tclk is a flow through version of ticlk; a variable propagation delay exists between these two signals. figure 50 transmit unipolar j2 stream tclk tdato e 4 e 5 bit 782 bit 783 bit 784 1 1 0 0 tohm frame alignment signal bit1 bit 2 bit 3 ticlk the transmit unipolar j2 stream diagram (figure 50) illustrates the unipolar j2 stream generation. the atm cell stream, along with valid j2 overhead bits is contained in tdato. the tohm output shown marks the j2 multi-frame boundary (the first frame-alignment bit of each j2 multi-frame) in the transmit stream. note: tclk is a flow through version of ticlk; a variable propagation delay exists between these two signals.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 306 document id: pmc-1990267, issue 3 figure 51 generic transmit stream tclk tdato overhead placeholder bits bit 5 bit 8 bit 7 bit 6 bit 1 bit 4 bit 3 bit 2 atm ce ll octet n +1 tohm tiohm ticlk tdato overhead placeholder bits bit 1 bit 4 bit 3 bit 2 bit 7 bit 8 bit 6 bit 4 bit 5 bit 5 bit 3 tohm tiohm ticlk bit logic 0: ticlk bit logic 1: atm ce ll octe t n bit 5 bit 6 bit 7 bit 8 atm ce ll octe t n ticlk atm ce ll octet n +1 the generic transmit stream diagram (figure 51) illustrates overhead indication positions when interfacing to a non-plcp based transmission system not supported by the suni-qjet. the overhead bit placeholder positions are indicated using the tiohm input. the atm cells presented in the tdato transmit stream are held off to include the overhead placeholders. the location of these placeholder positions is indicated by tohm. a downstream framer inserts the correct overhead information in the placeholder positions. the delay between tiohm and tohm is dependent on the state of the ticlk bit of the s/uni- jet transmit configuration register. if the ticlk bit is a logic zero, tohm is updated on the falling tclk edge. tclk is a flow-through version of ticlk and the propagation delay between ticlk and tclk may vary depending on specific configurations. if the ticlk bit is a logic one, tohm is presented on the fifth rising edge of ticlk after the rising edge which samples tiohm.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 307 document id: pmc-1990267, issue 3 figure 52 transmit ds3 overhead tohfp tohclk tohclk toh tohfp x1 f1 c1 f2 c2 f3 c3 ds3 m-frame period tohins the transmit ds3 overhead diagram (figure 52) shows the insertion of ds3 overhead bits using the toh input, along with the overhead insertion enable input, tohins. the tohfp output is set to logic one once per ds3 m-frame period (during the x1 bit position). in figure 52, the data sampled on toh during the x1, c1, f2, and c2 bit positions is inserted into the ds3 overhead bits in the transmit stream. the f1, f3, and c3 overhead bits are internally generated by the s/uni-jet . table 45 illustrates the overhead bit order on toh: table 45 ds3 transmit overhead bits ds3 overhead bits m-subframe 12345678 1 x 1 f 1 c 1 f 2 c 2 f 3 c 3 f 4 2x 2 f 1 c 1 f 2 c 2 f 3 c 3 f 4 3p 1 f 1 c 1 f 2 c 2 f 3 c 3 f 4 4p 2 f 1 c 1 f 2 c 2 f 3 c 3 f 4 5 m 1 f 1 c 1 f 2 c 2 f 3 c 3 f 4 6 m 2 f 1 c 1 f 2 c 2 f 3 c 3 f 4 7 m 3 f 1 c 1 f 2 c 2 f 3 c 3 f 4
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 308 document id: pmc-1990267, issue 3 figure 53 transmit g.832 e3 overhead tohfp tohclk toh g.832 frame period tohfp tohclk toh bit 1 em byte fa1 fa2 em tr ma nr gc bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 fa2 byte fa1 byte tohins tohins fa1 fa2 54 cycles bit 1 bit 2 the transmit g.832 e3 overhead diagram (figure 53) shows the insertion of g.832 e3 overhead bits using the toh input, along with the overhead insertion enable input, tohins. the tohfp output is set to logic one once per g.832 frame period (during the first bit position of the fa1 byte). in figure 53, the bit data sampled on toh during each byte position while tohins is logic one is inserted into the g.832 e3 overhead bits in the transmit stream. note: if an entire byte is to be replaced with data from the toh stream, tohins must be held logic one for the duration of that byte position. also note: the em byte behaves as an error mask, that is the binary value sampled on toh in the em byte location is not inserted directly into the transmit overhead but, rather, the value is xored with the calculated bip-8 and inserted in the transmit overhead. asserting tohins during the ?gaps? in the toh stream has no effect.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 309 document id: pmc-1990267, issue 3 figure 54 transmit g.751 e3 overhead tohfp tohclk toh g.751 frame period rai nat c11 c21 c31 c41 c12 c22 c32 c13 c23 c33 j1 j2 j3 c42 c43 j4 tohins rai rai ... ... ... 30 c y cles j4 ... the transmit g.751 e3 overhead diagram (figure 54) shows the insertion of g.751 overhead bits rai, the national use bit, and the stuff indication and opportunity bits using the toh input, along with the overhead insertion enable input, tohins. the tohfp output is set to logic one once per g.751 e3 frame period (during the rai bit position). in figure 54, the data sampled on toh during the rai, national use, or stuff bit positions while tohins is logic one is inserted into the g.751 e3 overhead bits in the transmit stream. the pyld&just bit in the e3 tran status and diagnostics options register has no affect on the insertion of the justification service and the tributary justification bits through the toh and the tohins inputs. figure 55 transmit j2 overhead ... ... ... ... ... ... ... ... m1 0 0 1 1 e5 e4 e3 e2 e1 ts97 ts98 ts97 ts98 ts97 j2 multi-frame period tohfp tohclk toh tohi ns the transmit j2 overhead diagram (figure 55) shows the insertion of j2 overhead bits using the toh and tohins inputs. the tohfp output is set to logic one once per j2 multiframe (for the first bit of ts97 in the first frame of the j2 multiframe). tohclk is a gapped clock which will pulse at a maximum instantaneous rate equal to the ticlk frequency. when tohins is a logic one, the toh input pin state replaces that generated within the j2 tran block. toh and tohins are sampled on the rising tohclk clock edge.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 310 document id: pmc-1990267, issue 3 figure 56 transmit plcp overhead tpohfp tpohclk f1 octet m1 octet m2 octet g1 octet b1 octet z1 octet z2 octet tpohclk b 5 b 4 b 6 b 3 b 7 b 2 tpoh b 1 b 8 b 8 b 1 tpohfp don't care tpohins f1 octet b1 octet the transmit plcp overhead diagram (figure 56) shows the insertion of the plcp path overhead bits using the tpoh input, along with overhead clock (tpohclk), and plcp frame position indicator (tpohfp). the path overhead octets are shifted in order with the most significant bit (bit 1) of each octet first. the number of growth octets (zn) in the plcp frame varies according to the selected plcp frame format (ds3, ds1, g.751 e3, or e1). the plcp frame position indicator (tpohfp) is set high once per plcp frame period, during bit 1 of the f1 octet, and indicates the transmit plcp frame timing. tpoh and tpohins are sampled using the rising edge of tpohclk. the bit presented on tpoh is only inserted into the path overhead if tpohins is asserted during the bit in question, or if the appropriate bit is set in the splt control register. the timing diagram above assumes that the srcb1 bit in the splt control register is programmed to logic zero, thereby selecting internal insertion of that octet.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 311 document id: pmc-1990267, issue 3 figure 57 framer mode ds3 transmit input stream tdati info 84 tfpi/tmfpi info 84 info 83 info 82 x1 info 2 info 1 x2 info 1info 2info 3 info 84 info 82 info 83 f4 info 82 info 83 tfpo/tmfpo ticlk figure 58 framer mode ds3 transmit input stream with tgapclk tgapclk tdati info 1 info 83 info 82 info 81 info 3 info 2 info 2 info 3 info 4 info 1 info 83 info 84 info 83 info 84 ticlk info 1 the framer mode ds3 transmit input stream diagrams (figure 57 and figure 58) show the expected format of the inputs tdati and tfpi/tmfpi along with ticlk and the output tfpo/tmfpo when the frmronly bit in the s/uni-jet configuration 1 register is set, and the s/uni-jet is configured for the ds3 transmit format. if the txmfpi register bit is logic zero, then tfpi is valid, and the s/uni-jet will expect tfpi to pulse for every ds3 overhead bit with alignment to tdati. if the txmfpi register bit is logic one, then tmfpi is valid, and the s/uni-jet will expect tmfpi to pulse once every ds3 m-frame with alignment to tdati. if the txmfpo register bit is logic zero, then tfpo is valid, and the s/uni-jet will pulse tfpo once every 85 ticlk cycles, providing upstream equipment with a reference ds3 overhead pulse. if the txmfpo register bit is logic one, then tmfpo is valid and the s/uni-jet will pulse tmfpo once every 4760 ticlk cycles, providing upstream equipment with a reference m- frame pulse. the alignment of tfpo or tmfpo is arbitrary. there is no set relationship between tfpo/tmfpo and tfpi/tmfpi. the tgapclk output is available in place of tfpo/tmfpo when the txgapen bit in the s/uni-jet configuration 2 register is set to logic one, as in figure 58. tgapclk remains high during the overhead bit positions. tdati is sampled on the falling edge of tgapclk. figure 59 framer mode ds3 receive output stream rdato info 84 rfpo/rmfpo info 84 info 83 info 82 x1 info 2 info 1 x2 info 1info 2info 3 info 84 info 82 info 83 f4 info 82 info 83 rovrhd rsclk]
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 312 document id: pmc-1990267, issue 3 figure 60 framer mode ds3 receive output stream with rgapclk rgapclk rdato info 84 info 84 info 83 info 82 info 2 info 1 info 1 info 2 info 3 info 84 info 82 info 83 info 82 info 83 info 84 the framer mode ds3 receive output stream diagrams (figure 59 and figure 60) show the format of the outputs rdato, rfpo/rmfpo, rsclk (and rgapclk), and rovrhd when the frmronly bit in the s/uni-jet configuration 1 register is set. figure 59 shows the data streams when the s/uni-jet is configured for the ds3 receive format. if the rxmfpo and 8krefo register bits are logic zero, rfpo is valid and will pulse high for one rsclk cycle on first bit of each m-subframe with alignment to the rdato data stream. if the rxmfpo register bit is a logic one (as shown in figure 59) and the 8krefo register bit is logic zero, rmfpo is valid and will pulse high on the x1 bit of the rdato data output stream. rovrhd will be high for every overhead bit position on the rdato data stream. as shown in figure 60 the rgapclk output is available in place of rsclk when the rxgapen bit in the s/uni-jet configuration 2 register is set to logic one. rgapclk remains high during the overhead bit positions and rdato does not change. figure 61 framer mode g.751 e3 transmit input stream tdati bit 1536 0 tfpi/tmfpi nat rai 11 1 10100 bit 1531 bit 1529 bit 1530 bit 1532 bit 1533 bit 1534 bit 1535 tfpo/tmfpo 0 bit13 ticlk figure 62 framer mode g.751 e3 transmit input stream with tgapclk tgapclk tdati bit 1536 bit 1531 bit 1529 bit 1530 bit 1532 bit 1533 bit 1534 bit 1535 bit14 ticlk bit13
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 313 document id: pmc-1990267, issue 3 the framer mode g.751 e3 transmit input stream diagrams (figure 61 and figure 62) show the expected format of the inputs tdati, tfpi/tmfpi, and ticlk and the output tfpo/tmfpo (and tgapclk) when the frmronly bit in the s/uni-jet configuration 1 register is set, and the s/uni-jet is configured for the e3 g.751 transmit format. tfpi or tmfpi pulses high for one ticlk cycle and is aligned to the first bit of the frame alignment signal in the g.751 e3 input data stream on tdati. tfpo or tmfpo will pulse high for one out of every 1536 ticlk cycles, providing upstream equipment with a reference frame pulse. the alignment of tfpo or tmfpo is arbitrary. there is no set relationship between tfpo/tmfpo and tfpi/tmfpi. the tgapclk output is available in place of tfpo/tmfpo when the txgapen bit in the s/uni- jet configuration 2 register is set to logic one, as in figure 62. tgapclk remains high during the overhead bit positions. tdati is sampled on the falling edge of tgapclk. figure 63 framer mode g.751 e3 receive output stream rdato bit 1536 0 rfpo/rmfpo nat rai 1 1 1 10100 bit 1531 bit 1529 bit 1530 bit 1532 bit 1533 bit 1534 bit 1535 rovrhd 0 bit13 rsclk figure 64 framer mode g.751 e3 receive output stream with rgapclk rgapclk rdato bit 1536 bit 1531 bit 1529 bit 1530 bit 1532 bit 1533 bit 1534 bit 1535 bit13 the framer mode g.751 e3 receive output stream diagrams (figure 63 and figure 64) show the format of the outputs rdato, rfpo/rmfpo, rsclk (and rgapclk), and rovrhd when the frmronly and the 8krefo bits in the s/uni-jet configuration 1 register are set to logic one and logic zero respectively. figure 63 shows the data streams when the s/uni-jet is configured for the e3 g.751 receive format. rfpo or rmfpo pulses high for one rsclk cycle and is aligned to the first bit of the framing alignment signal in the g.751 e3 output data stream on rdato. rovrhd will be high for every overhead bit position on the rdato data stream. if the pyld&just register bit in the e3 frmr maintenance options register is set to logic zero, the c jk and p k bits in the rdato stream will be marked as overhead bits. if the pyld&just register bit is set to logic one, the c jk and p k bits in the rdato stream will be marked as payload. the rgapclk output is available in place of rsclk when the rxgapen bit in the s/uni-jet configuration 2 register is set to logic one. rgapclk remains high during the overhead bit positions as shown in figure 64.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 314 document id: pmc-1990267, issue 3 figure 65 framer mode g.832 e3 transmit input stream tdati oct 530 8 tfpi/tmfpi oct n 3 oct n 2 oct n 1 fa1 1 fa1 4 fa1 3 fa1 2 fa1 5 fa1 6 fa1 7 fa1 8 oct 530 3 oct 530 1 oct 530 2 oct 530 4 oct 530 5 oct 530 6 oct 530 7 tfpo/tmfpo ticlk figure 66 framer mode g.832 e3 transmit input stream with tgapclk tgapclk tdati oct 530 8 oct n 3 oct n 2 oct n 1 oct 530 3 oct 530 1 oct 530 2 oct 530 4 oct 530 5 oct 530 6 oct 530 7 ticlk the framer mode g.832 e3 transmit input stream diagrams (figure 65 and figure 66) show the expected format of the inputs tdati, tfpi/tmfpi, and ticlk and the output tfpo/tmfpo (and tgapclk) when the frmronly bit in the s/uni-jet configuration 1 register is set, and the s/uni-jet is configured for the e3 g.832 transmit format. tfpi or tmfpi pulses high for one ticlk cycle and is aligned to the first bit of the fa1 byte in the g.832 e3 input data stream on tdati. tfpo or tmfpo will pulse high for one out of every 4296 ticlk cycles, providing upstream equipment with a reference frame pulse. the alignment of tfpo or tmfpo is arbitrary. there is no set relationship between tfpo/tmfpo and tfpi/tmfpi. the tgapclk output is available in place of tfpo/tmfpo when the txgapen bit in the s/uni- jet configuration 2 register is set to logic one, as in figure 66. tgapclk remains high during the overhead bit positions. tdati is sampled on the falling edge of tgapclk. figure 67 framer mode g.832 e3 receive output stream rdato oct 530 8 rfpo/rmfpo oct 1 2 oct 1 1 fa2 8 fa1 1 fa1 4 fa1 3 fa1 2 fa1 5 fa1 6 fa1 7 fa1 8 oct 530 3 oct 530 1 oct 530 2 oct 530 4 oct 530 5 oct 530 6 oct 530 7 rovrhd rsclk figure 68 framer mode g.832 e3 receive output stream with rgapclk rgapclk rdato oct 530 8 oct 1 2 oct 1 1 oct 530 3 oct 530 1 oct 530 2 oct 530 4 oct 530 5 oct 530 6 oct 530 7
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 315 document id: pmc-1990267, issue 3 the framer mode g.832 e3 receive output stream diagrams (figure 67 and figure 68) show the format of the outputs rdato, rfpo/rmfpo, rsclk (and rgapclk), and rovrhd when the frmronly bit in the s/uni-jet configuration 1 register is set. figure 67 shows the data streams when the s/uni-jet is configured for the e3 g.832 receive format. rfpo or rmfpo pulses high for one rsclk cycle and is aligned to the first bit of the fa1 byte in the g.832 e3 output data stream on rdato. rovrhd will be high for every overhead bit position on the rdato data stream. the rgapclk output is available in place of rsclk when the rxgapen bit in the s/uni-jet configuration 2 register is set to logic one. rgapclk remains high during the overhead bit positions as shown in figure 68. figure 69 framer mode j2 transmit input stream tdati tfpi/tmfpi 10 1 ts98 8 x1 x2 x3 e1 tfpo/tmfpo ts98 8 ts98 7 ts98 6 ts98 8 ts98 7 ts98 6 tsn 6 tsn 7 tsn 8 ticlk figure 70 framer mode j2 transmit input stream with tgapclk tgapclk tdati ts98 8 ts1 1 ts98 8 ts98 7 ts1 1 ts98 8 ts98 7 tsn 6 tsn 8 ticlk ts1 1 tsn 7 the framer mode j2 transmit input stream diagrams (figure 69 and figure 70) show the expected format of the inputs tdati, tfpi/tmfpi, and ticlk and the output tfpo/tmfpo (and tgapclk) when the frmronly bit in the s/uni-jet configuration 1 register is set, and the s/uni-jet is configured for the j2 transmit format. if the txmfpi register bit is logic zero, then tfpi is valid (as shown in figure 69). the s/uni-jet will expect tfpi to pulse once every j2 frame with alignment to the first frame alignment bit on tdati. if the txmfpi register bit is logic one, then tmfpi is valid. the s/uni-jet will expect tmfpi to pulse once every j2 multi-frame with alignment to the first frame alignment bit on tdati. if the txmfpo register bit is logic zero, then tfpo is valid. the s/uni-jet will pulse tfpo once every 789 ticlk cycles, providing upstream equipment with a reference frame pulse. if the txmfpo register bit is logic one, then tmfpo is valid and the s/uni-jet will pulse tmfpo once every 3156 ticlk cycles, providing upstream equipment with a reference multi-frame pulse. the alignment of tfpo or tmfpo is arbitrary. there is no set relationship between tfpo/tmfpo and tfpi/tmfpi. the tgapclk output is available in place of tfpo/tmfpo when the txgapen bit in the s/uni-jet configuration 2 register is set to logic one, as in figure 70. tgapclk remains high during the overhead bit positions. tdati is sampled on the falling edge of tgapclk.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 316 document id: pmc-1990267, issue 3 figure 71 framer mode j2 receive output stream rdato rfpo/rmfpo 10 1 ts96 8 e1 rovrhd ts1 1 m1 0 ts97 8 ts97 7 ts97 6 ts97 6 ts97 7 ts97 8 rsclk ts97 3 ts97 2 ts97 1 figure 72 framer mode j2 receive output stream with rgapclk rgapclk rdato ts96 8 ts1 1 ts96 8 ts96 7 ts96 6 ts90 6 ts90 7 ts90 8 ts96 8 the framer mode j2 receive output stream diagrams (figure 71 and figure 72) show the format of the outputs rdato, rfpo/rmfpo, rsclk (and rgapclk), and rovrhd when the frmronly bit in the s/uni-jet configuration 1 register is set. figure 71 shows the data streams when the s/uni-jet is configured for the j2 receive format. if the rxmfpo register bit is a logic zero, rfpo is valid and will pulse high for one rsclk cycle once each j2 frame with alignment to the first frame alignment bit on the rdato data stream (as shown in figure 71). if the rxmfpo register bit is a logic one, rmfpo is valid and will pulse high once each j2 multi- frame aligned to the first frame alignment bit on the rdato data output stream. rovrhd will be high for every overhead bit position on the rdato data stream. the rgapclk output is available in place of rsclk when the rxgapen bit in the s/uni-jet configuration 2 register is set to logic one. rgapclk remains high during the overhead bit positions as shown in figure 72.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 317 document id: pmc-1990267, issue 3 figure 73 multi-phy polling and addressing transmit cell interface tca tsoc tdat[15 :0] tprty w (n-6) w (n-5) w1 w2 w3 w (n-4) w (n-3) w (n-2) w (n-1) w (n) w (n-7) w4 x x tfclk tenb tadr[2:0] ca(a) ca(b) ca(c) ca(b) ab 1fh c 1fh b 1fh a 1fh c 1fh ca(a) x x dtca[d] tc a le vel 0=0 figure 73 is an example of the multi-phy polling and selection sequence supported by the s/uni-jet . "a", "b", "c", and ?d? represent any arbitrary address values of phy devices which may be occupied by the s/uni-jet . the atm layer device is not restricted in its polling order. initially phy ?d? is accepting a cell and the direct tca for that phy is shown as dtca[d]. the effect of tcalevel0 is indicated with a dashed line in the figure. the phy associated with address "a" indicates it cannot accept a cell, but phy "b" indicates it is willing to accept a cell. as a result, the atm layer places address "b" on tadr[2:0] the cycle before tenb is asserted to select phy "b" as the next cell destination. in this example, the phy "c" status is ignored. the atm layer device is not constrained to select the latest phy polled. as soon as the cell transfer is started, the polling process may be restarted. the data on tdati (w1, w2, ..) may be 8-bit or 16-bits wide, depending on the setting of the atm8 input. during multi-phy operation, several phy layer devices share the tca signal. as a result, this signals must be tri-stated in all phy devices which have not been selected for polling by the atm layer. the value of tadr[2:0] selects the phy being polled for the tca signal, and all devices not corresponding to this address must tri-state its tca output. this multi-phy operation is directly supported by the s/uni-jet .
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 318 document id: pmc-1990267, issue 3 figure 74 multi-phy polling and addressing receive cell interface rca rsoc rdat[15:0] rprty w (n-7) w (n-6) w (n-5) w1 w2 w3 w (n-4) w (n-3) w (n-2) w (n-1) w (n) rfclk renb radr[2:0] ca(a) ca(b) ca(c) ca(b) ab 1fh c 1fh b x d 1fh e 1fh ca(d) x 1fh drca[d] rc a level0=0 figure 74 shows an example of the multi-phy polling and selection sequence supported by the s/uni-jet . "a", "b", "c", "d", and "e" represent any arbitrary address values which may be occupied by the s/uni-jet . initially cell data is being received from phy ?d,? and the drca[d] signal shows how the drca[x] signals behave based on the value of the rcalevel0 register bit(s). the atm layer device is not restricted in its polling order. the phy associated with address "a" indicates it does not have a cell available, but phy "b" indicates that it does. as a result, the atm layer places address "b" on radr[2:0] the cycle before renb is asserted to select phy "b" as the next cell source. in this example, phy "c"s status is ignored. the atm layer device is not constrained to select the latest phy polled. as soon as the cell transfer is started, the polling process may be restarted. the data on rdat (w1, w2, ..) may be 8-bit or 16-bits wide, depending on the setting of the atm8 input. during multi-phy operation, several phy layer devices share the rdat[15:0], rsoc, rprty, and rca signals. as a result, these signals must be tri-stated in all phy devices which have not been selected for reading or polling by the atm layer. selection of which phy layer device is being read is made by the value on radr[2:0] the cycle before renb is asserted and affects the rdat[15:0], rsoc, and rprty signals. the value of radr[2:0] selects the phy being polled for the rca signal, and all devices not corresponding to this address must tri-state its rca output. these multi-phy operations are directly supported by the s/uni-jet.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 319 document id: pmc-1990267, issue 3 15 absolute maximum ratings table 46 absolute maximum ratings ambient temperature under bias -55c to +125c storage temperature -65c to +150c supply vdd with respect to gnd -0.3 v to 4.6 v voltage on bias with respect to gnd vdd - 0.3 v to 5.5 v voltage on any pin -0.3 v to bias +0.3 v static discharge voltage 1000 v latch-up current 100 ma dc input current 20 ma lead temperature +230c absolute maximum junction temperature +150c
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 320 document id: pmc-1990267, issue 3 16 d.c. characteristics t a = -40c to +85c, v dd = 3.3v 10%, v dd < bias < 5.5 v (typical conditions: t a = 25c, v dd = 3.3 v, v bias = 5 v) table 47 dc characteristics symbol parameter min typ max units conditions v dd power supply 2.97 3.3 3.63 volts bias 5 v tolerant bias vdd 5.0 5.5 volts i bias current into 5 v bias 6.0 a v bias = 5.5 v v il input low voltage 0 0.8 volts guaranteed input low voltage. v ih input high voltage 2.0 bias volts guaranteed input high voltage. v ol output or bi-directional low voltage 0.23 0.4 volts guaranteed output low voltage at vdd=2.97 v and i ol =maximum rated for pad. 4, 5, 6 v oh output or bi-directional high voltage 2.4 2.93 volts guaranteed output high voltage at vdd=2.97 v and i oh =maximum rated current for pad. 4, 5, 6 v t- reset input low voltage 0.8 volts applies to rstb, trstb, ticlk[4:1], rclk[4:1], tfclk, rfclk, tck, tdi, tms, and ref8ki. v t+ reset input high voltage 2.0 volts applies to rstb, trstb, ticlk[4:1], rclk[4:1], tfclk, rfclk, tck, tdi, tms, and ref8ki. v th reset input hysteresis voltage 0.5 volts applies to rstb, trstb, ticlk[4:1], rclk[4:1], tfclk, rfclk, tck, tdi, tms, and ref8ki. i ilpu input low current -100 -60 -10 a v il = gnd. 1, 3 i ihpu input high current -10 0 +10 a v ih = v dd . 1. 3 i il input low current -10 0 +10 a v il = gnd. 2, 3 i ih input high current -10 0 +10 a v ih = v dd . 2, 3 c in input capacitance 6 pf t a =25c, f = 1 mhz c out output capacitance 6 pf t a =25c, f = 1 mhz c io bi-directional capacitance 6pf t a =25c, f = 1 mhz iddop1 operating current 165 ma vdd = 3.63 v, outputs unloaded (ds3/plcp mode)
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 321 document id: pmc-1990267, issue 3 symbol parameter min typ max units conditions iddop2 operating current 20 ma vdd = 3.63 v, outputs unloaded (t1/e1 plcp mode) iddop3 operating current 170 ma vdd = 3.63 v, outputs unloaded (ds3 atm mode) i ddop4 operating current 150 ma v dd = 3.63 v, outputs unloaded (e3 atm mode) i ddop5 operating current 40 ma v dd = 3.63 v, outputs unloaded (j2 atm mode) i ddop6 operating current 150 ma v dd = 3.63 v, outputs unloaded (52 mbit/s arbitrary framing format with atm direct mapping) i ddop7 operating current 230 ma v dd = 3.63 v, outputs unloaded (ds3 framer only) i ddop8 operating current 120 ma v dd = 3.63 v, outputs unloaded (e3 framer only) i ddop9 operating current 30 ma v dd = 3.63 v, outputs unloaded (j2 framer only) notes 1. input pin or bi-directional pin with internal pull-up resistor. 2. input pin or bi-directional pin without internal pull-up resistor 3. negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). 4. the utopia interface outputs, rdat[15:0], rprty, rca, drca, rsoc, tca, and dtca, have 12 ma drive capability. 5. the outputs tclk, tpos/tdato, tneg/tohm, tpohfp/tfpo/tmfpo/tgapclk, lcd/rdato, rpoh/rovrhd, rpohclk/rsclk/rgapclk, and ref8ko/rpohfp/rfpo/rmfpo have 6 ma drive capability. 6. the data bus outputs, d[7:0], and all outputs not specified above have 3 ma drive capability.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 322 document id: pmc-1990267, issue 3 17 microprocessor interface timing characteristics (t a = -40c to +85c, v dd = 3.3 v 10%) table 48 microprocessor interface read access (figure 75) symbol parameter min max units ts ar address to valid read set-up time 10 ns th ar address to valid read hold time 5 ns ts alr address to latch set-up time 10 ns th alr address to latch hold time 10 ns tv l valid latch pulse width 5 ns ts lr latch to read set-up 0 ns th lr latch to read hold 5 ns tp rd valid read to valid data propagation delay 70 ns tz rd valid read negated to output tri-state 20 ns tz inth valid read negated to output tri-state 50 ns figure 75 microprocessor interface read timing tz rd valid data d[7:0] tp rd ts ar th ar (csb+rdb) a[10:0] valid address ale tv l ts alr ts lr th alr th lr tz inth
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 323 document id: pmc-1990267, issue 3 notes 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum output propagation delays are measured with a 100 pf load on the microprocessor interface data bus, (d[7:0]). 3. a valid read cycle is defined as a logical or of the csb and the rdb signals. 4. in non-multiplexed address/data bus architectures, ale should be held high so parameters ts alr , th alr , tv l , ts lr , and th lr are not applicable. 5. parameter th ar is not applicable if address latching is used. 6. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 7. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. table 49 microprocessor interface write access (figure 76) symbol parameter min max units ts aw address to valid write set-up time 10 ns ts dw data to valid write set-up time 20 ns ts alw address to latch set-up time 10 ns th alw address to latch hold time 10 ns tv l valid latch pulse width 5 ns ts lw latch to write set-up 0 ns th lw latch to write hold 5 ns th dw data to valid write hold time 5 ns th aw address to valid write hold time 5 ns tv wr valid write pulse width 40 ns
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 324 document id: pmc-1990267, issue 3 figure 76 microprocessor interface write timing th dw valid data d[7:0] tv wr ts aw th aw ts dw (csb+w rb) a[10:0] valid address ale tv l ts alw ts lw th alw th lw notes 1. a valid write cycle is defined as a logical or of the csb and the wrb signals. 2. in non-multiplexed address/data bus architectures, ale should be held high so parameters ts alw , th alw , tv l , ts lw , and th lw are not applicable. 3. parameter th aw is not applicable if address latching is used. 4. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 5. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 325 document id: pmc-1990267, issue 3 18 a.c. timing characteristics (t a = -40c to +85c, v dd = 3.3v 10%) table 50 rstb timing (figure 77) symbol description min typical max units tv rstb rstb pulse width 4 100 ns figure 77 rstb timing rstb tv rstb table 51 transmit atm cell interface timing (figure 78) symbol description min max units f tfclk tfclk frequency 52 mhz d tfclk tfclk duty cycle 40 60 % ts tfclk tenb, tadr[2:0], tdati[15:0], tprty, and tsoc set-up time to tfclk 3ns th tfclk tenb, tadr[2:0], tdati[15:0], tprty, and tsoc hold time to tfclk 1ns tp tca tfclk high to dtca and tca valid 1 12 ns tz tca tfclk high to tca tri-state 1 10 ns tzb tca tfclk high to tca driven 1 ns
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 326 document id: pmc-1990267, issue 3 figure 78 transmit atm cell interface timing tfclk tenb tadr[2.0] tdat[15.0] tprty tsoc dtca/tca tca tca ts tfclk th tfclk ts tfclk th tfclk ts tfclk th tfclk ts tfclk th tfclk ts tfclk th tfclk tca tp tca tz tzb tca
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 327 document id: pmc-1990267, issue 3 table 52 receive atm cell interface timing (figure 79) symbol description min max units f rfclk rfclk frequency 52 mhz d rfclk rfclk duty cycle 40 60 % ts rfclk renb and radr[2:0] set-up time to rfclk 3 ns th rfclk renb and radr[2:0] hold time to rfclk 1 ns tp rfclk rfclk high to output valid 1 12 ns tz rfclk rfclk high to output tri-state 1 12 ns tzb rfclk rfclk high to output driven 1 ns
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 328 document id: pmc-1990267, issue 3 figure 79 receive atm cell interface timing rfclk th rfclk ts rfclk renb radr[2:0] rfclk valid data tz rfclk renb rdat[15:0 ] rprty rsoc rca tzb rfclk tp rfclk tp rfclk rca drca
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 329 document id: pmc-1990267, issue 3 table 53 transmit interface timing (figure 80) symbol description min typ max units f ticlk ticlk frequency: ds3 framer (tfrm[1:0] = 00) 52 mhz e3 framer (tfrm[1:0] = 01) 35 j2 framer (tfrm[1:0] = 10) 7 framer bypass (tfrm[1:0] = 11) 52 t0 ticlk ticlk minimum pulse width low: ds3 framer (tfrm[1:0] = 00) 7.7 ns e3 framer (tfrm[1:0] = 01) 11 j2 framer (tfrm[1:0] = 10) 57 framer bypass (tfrm[1:0] = 11) 7.7 t1 ticlk ticlk minimum pulse width high: ds3 framer (tfrm[1:0] = 00) 7.7 ns e3 framer (tfrm[1:0] = 01) 11 j2 framer (tfrm[1:0] = 10) 57 framer bypass (tfrm[1:0] = 11) 7.7 ts tiohm tiohm/tfpi/tmfpi to ticlk set-up time 5 ns th tiohm tiohm/tfpi/tmfpi to ticlk hold time 1 ns ts tdati tdati to ticlk set-up time 5 ns th tdati tdati to ticlk hold time 1 ns ts ltiohm tiohm/tfpi/tmfpi to rclk set-up time (loopt=1) 5ns th ltiohm tiohm/tfpi/tmfpi to rclk hold time (loopt=1) 1ns ts ltdati tdati to rclk set-up time (loopt=1) 5 ns th ltdati tdati to rclk hold time (loopt=1) 1 ns tp tfpo ticlk to tfpo/tmfpo[x] prop delay, or rclk to tfpo/tmfpo prop delay when loop timing is used. 216ns ts tgap tdati to tgapclk set-up time 3 ns th tgap tdati to tgapclk hold time 2 ns tw ref8ki ref8ki pulse width 415ns ts toh toh to tohclk set-up time 20 ns th toh toh to tohclk hold time 20 ns ts tohins tohins to tohclk set-up time 20 ns th tohins tohins to tohclk hold time 20 ns tp tohfp tohclk to tohfp prop delay -15 20 ns
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 330 document id: pmc-1990267, issue 3 symbol description min typ max units ts tpoh tpoh to tpohclk set-up time 20 ns th tpoh tpoh to tpohclk hold time 20 ns ts tpohin tpohins to tpohclk set-up time 20 ns th tpohin tpohins to tpohclk hold time 20 ns tp tpohfp tpohclk to tpohfp prop delay -15 20 ns tp tpos tclk edge to tpos/tdato prop delay -1 4.5 ns tp tneg tclk edge to tneg/tohm prop delay -1 4.5 ns tp tpos2 ticlk high to tpos/tdato prop delay 2 13 ns tp tneg2 ticlk high to tneg/tohm prop delay 2 13 ns figure 80 transmit interface timing ts tiohm th tiohm tiohm/tfpi/tmfpi ticlk/rclk th ltiohm ts ltiohm ts ltdati th tdati tdati th ltdati ts tdati ticlk/rclk tp tfpo tfpo/tmfpo ticlk / rclk
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 331 document id: pmc-1990267, issue 3 ts tgap th tgap tdati tgapclk ref8ki tw ref8ki ts tohins th tohins tohins ts toh th toh toh tohclk tp tohfp tohfp tohclk
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 332 document id: pmc-1990267, issue 3 ts tpoh th tpoh tpoh ts tpohin th tpohin tpohins tpohclk tp tpohfp tpohfp tpohclk
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 333 document id: pmc-1990267, issue 3 tp tneg tne g/t ohm ticl k tp tpos tpos /td ato tcl k ticlk=0, tclkinv=0 tp tneg tne g/t ohm ticl k tp tpos tpos /td ato tcl k ticlk=0, tclkinv=1 tp tneg2 tne g/t ohm ticl k tp tpos2 tpos /td ato tcl k ticlk=1, tclkinv=x
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 334 document id: pmc-1990267, issue 3 table 54 receive interface timing (figure 81) symbol description min max units f rclk rclk frequency: ds3 framer (rfrm[1:0] = 00) 52 mhz e3 framer (rfrm[1:0] = 01) 35 j2 framer (rfrm[1:0] = 10) 7 framer bypass (rfrm[1:0] = 11) 52 mhz t0 rclk rclk minimum pulse width low: ds3 framer (rfrm[1:0] = 00) 7.7 ns e3 framer (rfrm[1:0] = 01) 11 j2 framer (rfrm[1:0] = 10) 57 framer bypass (rfrm[1:0] = 11) 7.7 t1 rclk rclk minimum pulse width high: ds3 framer (rfrm[1:0] = 00) 7.7 ns e3 framer (rfrm[1:0] = 01) 11 j2 framer (rfrm[1:0] = 10) 57 framer bypass (rfrm[1:0] = 11) 7.7 ts rpos rpos/rdati set-up time 4 ns th rpos rpos/rdati hold time 1 ns ts rneg rneg/rohm set-up time 4 ns th rneg rneg/rohm hold time 1 ns tp rrdato rsclk/rgapclk rising edge to rdato prop delay 213ns tp rrfpo rsclk rising edge to rfpo/rmfpo prop delay 1 13 ns tp rrovrhd rsclk rising edge to rovrhd prop delay 1 13 ns tp frdato rsclk/rgapclk falling edge to rdato prop delay -2 10 ns tp frfpo rsclk falling edge to rfpo/rmfpo prop delay -2 10 ns tp frovrhd rsclk falling edge to rovrhd prop delay -2 10 ns tp roh rohclk low to roh prop delay -15 20 ns tp rohfp rohclk low to rohfp prop delay -15 20 ns tp rpoh rpohclk low to rpoh prop delay -15 20 ns tp rpohfp rpohclk low to rpohfp prop delay -15 20 ns
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 335 document id: pmc-1990267, issue 3 figure 81 receive interface timing ts rpos th rpos rpos/rdati rclk ts rneg th rneg rneg/rohm tp frd a to rdato tp frfpo rfpo/rmfpo rsclk/rgapclk tp frovrhd rovrhd tp rrda to tp rrfpo tp rrovrhd
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 336 document id: pmc-1990267, issue 3 tp roh roh tp rohfp rohfp rohclk tp rpoh rpoh tp rpohfp rpohfp rpohclk table 55 jtag port interface (refer to figure 82) symbol description min typical max units t1 tck tck high pulse width 5ns t0 tck tck low pulse width 5 100 ns ts tms , ts tdi tms and tdi set-up time to tck 150 ns th tms , th tdi tms and tdi hold time to tck 250 ns tp tdo tck low to tdo valid 6,7 2 50 ns tv trstb trstb minimum pulse width 4,5 100 ns
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 337 document id: pmc-1990267, issue 3 figure 82 jtag port interface timing ts tms th tms tms tck ts tdi th tdi tdi tp tdo tdo tck tck t0 tck t1 trstb tv trstb notes (on input timing) 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 2. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. 3. it is recommended that the load on tgapclk[x] be kept less than 50pf. a larger load on these pins may result in functional failures. 4. this parameter is guaranteed by design. no production tests are done on this parameter. 5. high pulse width is measured from the 1.4 volt points of the rise and fall ramps. low pulse width is measured from the 1.4 volt points of the fall and rise ramps.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 338 document id: pmc-1990267, issue 3 notes (on output timing) 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum and minimum output propagation delays are measured with a 50 pf load on the outputs.
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 339 document id: pmc-1990267, issue 3 19 ordering and thermal information table 56 packaging information part no. description PM7347-BI 256-pin ball grid array (sbga) table 57 thermal information part no. ambient temperature theta ja theta jc PM7347-BI -40c to 85c 19 c/w 5 c/w
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 340 document id: pmc-1990267, issue 3 20 mechanical information die side bottom view a l a e p v u n m 10 15 14 13 12 11 e b corner a1 ball 1 9 8 7 6 5 4 3 2 e h k j g f b d c a d1, m 1 16 17 18 19 20 r t w e1, n 0.90 0.60 27 x 27 x 1.45 mm package type: max. nom. 1.58 min. dim. 1.32 a body size: 256 pin thermal ball grid array 0.70 0.88 0.82 27.10 27.00 24.23 24.13 0.56 a1 0.76 a2 26.90 d 24.03 d1 1.27 ee1 m,n e 0.15 aaa b 1.45 0.63 26.90 27.00 27.10 24.03 24.13 24.23 20x20 0.75 0.30 0.20 0.50 0.15 0.35 ccc bbb ddd 0.20 p 0.33 0.15 3) dimension bbb denotes parallel 4) dimension ccc denotes flatness 2) dimension aaa denotes coplanarity notes: 1) all dimensions in millimeter. a-a section view ddd p top view 0.127 a 0.127 a d e -b- -a- .30 a1 ball a1 ball i.d. ink mark a c a s s b a side view a1 a2 seating plane aaa bbb -c- c ccc y corner
s/uni?-jet data sheet released proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 341 document id: pmc-1990267, issue 3 notes

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